ATXMEGA128A1-CU Atmel, ATXMEGA128A1-CU Datasheet - Page 90
![MCU AVR 128K FLASH 1.6V 100-CBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATXMEGA128A1-CU
Manufacturer Part Number
ATXMEGA128A1-CU
Description
MCU AVR 128K FLASH 1.6V 100-CBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet
1.ATAVRONEKIT.pdf
(113 pages)
Specifications of ATXMEGA128A1-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATXMEGA128x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
78
Number Of Timers
8
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT, ATQT600
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 12-bit)
On-chip Dac
2 (2-ch x 12-bit)
Package
100CBGA
Device Core
AVR
Family Name
XMEGA
Maximum Speed
32 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATXMEGA128A1-CU
Manufacturer:
Atmel
Quantity:
33
Part Number:
ATXMEGA128A1-CU
Manufacturer:
AT
Quantity:
20 000
35. Errata
35.1
8067M–AVR–09/10
ATxmega128A1 rev. H
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Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
The ADC has up to ±2 LSB inaccuracy
ADC gain stage output range is limited to 2.4 V
Sampling speed limited to 500 ksps for supply voltage below 2.0V
ADC Event on compare match non-functional
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
The input difference between two succeeding ADC samples is limited by VREF
Increased noise when using internal 1.0V reference at low temperature
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
BODACT fuse location is not correct
Sampled BOD in Active mode will cause noise when bandgap is used as reference
DAC has up to ±10 LSB noise in Sampled Mode
DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
DAC refresh may be blocked in S/H mode
Conversion lost on DAC channel B in event triggered mode
Both DFLLs and both oscillators have to be enabled for one to work
Access error when multiple bus masters are accessing SDRAM
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
Low level interrupt triggered when pin input is disabled
JTAG enable does not override Analog Comparator B output
NMI Flag for Crystal Oscillator Failure automatically cleared
Flash Power Reduction Mode can not be enabled when entering sleep
Some NVM Commands are non-functional
Crystal start-up time required after power-save even if crystal is source for RTC
Setting PRHIRES bit makes PWM output unavailable
Accessing EBI address space with PREBI set will lock Bus Master
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI, the minimum I2C SCL low time could be violated in Master Read mode
TWI address-mask feature is non-functional
TWI, a general address call will match independent of the R/W-bit value
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag erroneously read as set
WDR instruction inside closed window will not issue reset
XMEGA A1
90