ATXMEGA128A1-CU Atmel, ATXMEGA128A1-CU Datasheet - Page 98
![MCU AVR 128K FLASH 1.6V 100-CBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATXMEGA128A1-CU
Manufacturer Part Number
ATXMEGA128A1-CU
Description
MCU AVR 128K FLASH 1.6V 100-CBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet
1.ATAVRONEKIT.pdf
(113 pages)
Specifications of ATXMEGA128A1-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATXMEGA128x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
78
Number Of Timers
8
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT, ATQT600
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 12-bit)
On-chip Dac
2 (2-ch x 12-bit)
Package
100CBGA
Device Core
AVR
Family Name
XMEGA
Maximum Speed
32 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATXMEGA128A1-CU
Manufacturer:
Atmel
Quantity:
33
Part Number:
ATXMEGA128A1-CU
Manufacturer:
AT
Quantity:
20 000
8067M–AVR–09/10
39. Clearing TWI Stop Interrupt Flag may lock the bus
40. TWI START condition at bus timeout will cause transaction to be dropped
41. TWI Data Interrupt Flag erroneously read as set
Problem fix/Workaround
Clear the flag in software after address interrupt.
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
{
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
}
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
)
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
if ( !(COMMS_PORT.IN & PIN1_bm) )
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
break;
XMEGA A1
98