ATMEGA640V-8CU Atmel, ATMEGA640V-8CU Datasheet - Page 301
![IC MCU AVR 64K FLASH 100-CBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATMEGA640V-8CU
Manufacturer Part Number
ATMEGA640V-8CU
Description
IC MCU AVR 64K FLASH 100-CBGA
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA640V-8CU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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26.7
26.8
26.9
26.9.1
2549M–AVR–09/10
Using the JTAG Programming Capabilities
Bibliography
On-chip Debug Related Register in I/O Memory
OCDR – On-chip Debug Register
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
•
•
•
•
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section
For more information about general Boundary-scan, the following literature can be consulted:
•
•
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Bit
0x31 (0x51)
Read/Write
Initial Value
Flash programming and verifying.
EEPROM programming and verifying.
Fuse programming and verifying.
Lock bit programming and verifying.
IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,
1992.
MSB/IDRD
R/W
7
0
R/W
6
0
ATmega640/1280/1281/2560/2561
“Programming via the JTAG Interface” on page
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
LSB
R/W
0
0
354.
OCDR
301
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