ATMEGA1281V-8MU Atmel, ATMEGA1281V-8MU Datasheet - Page 356
ATMEGA1281V-8MU
Manufacturer Part Number
ATMEGA1281V-8MU
Description
IC MCU AVR 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1281V-8MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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29.9.4
29.9.5
29.9.6
29.9.7
2549M–AVR–09/10
PROG_COMMANDS (0x5)
PROG_PAGELOAD (0x6)
PROG_PAGEREAD (0x7)
Data Registers
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as Data Register. The active
states are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs
of the Programming Command Register. The active states are the following:
•
•
The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port.
An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs
of the Programming Command Register. The active states are the following:
•
•
The Data Registers are selected by the JTAG instruction registers described in section
gramming Specific JTAG Instructions” on page
programming operations are:
•
•
•
•
Capture-DR: The result of the previous command is loaded into the Data Register.
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
Update-DR: The programming command is applied to the Flash inputs.
Run-Test/Idle: One clock cycle is generated, executing the applied command.
Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
Update-DR: The content of the Flash Data Byte Register is copied into a temporary register.
A write sequence is initiated that within 11 TCK cycles loads the content of the temporary
register into the Flash page buffer. The AVR automatically alternates between writing the low
and the high byte for each new Update-DR state, starting with the low byte for the first
Update-DR encountered after entering the PROG_PAGELOAD command. The Program
Counter is pre-incremented before writing the low byte, except for the first written byte. This
ensures that the first data is written to the address set up by PROG_COMMANDS, and
loading the last location in the page buffer does not make the program counter increment
into the next page.
Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte
Register. The AVR automatically alternates between reading the low and the high byte for
each new Capture-DR state, starting with the low byte for the first Capture-DR encountered
after entering the PROG_PAGEREAD command. The Program Counter is post-incremented
after reading each high byte, including the first read byte. This ensures that the first data is
captured from the first address set up by PROG_COMMANDS, and reading the last location
in the page makes the program counter increment into the next page.
Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
Reset Register.
Programming Enable Register.
Programming Command Register.
Flash Data Byte Register.
ATmega640/1280/1281/2560/2561
354. The Data Registers relevant for
“Pro-
356
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