ATMEGA128-16MU Atmel, ATMEGA128-16MU Datasheet - Page 83

• Manufacturer Part Number: ATMEGA128-16MU
• Description: IC AVR MCU 128K 16MHZ 5V 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/JTAG/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 64MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2467V–AVR–02/11
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 – ADC0 – Port F, Bit 3..0
Analog to Digital Converter, Channel 3..0.
Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Table 44. Overriding Signals for Alternate Functions in PF3..PF0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PF7/ADC7/TDI
JTAGEN
1
JTAGEN
0
0
0
JTAGEN
0
–
TDI/ADC7 INPUT
PF3/ADC3
0
0
0
0
0
0
0
0
–
ADC3 INPUT
PF6/ADC6/TDO
JTAGEN
0
JTAGEN
SHIFT_IR +
SHIFT_DR
JTAGEN
TDO
JTAGEN
0
–
ADC6 INPUT
PF2/ADC2
0
0
0
0
0
0
0
0
–
ADC2 INPUT
.
PF5/ADC5/TMS
JTAGEN
1
JTAGEN
0
0
0
JTAGEN
0
–
TMS/ADC5
INPUT
PF1/ADC1
ADC1 INPUT
0
0
0
0
0
0
0
0
–
PF4/ADC4/TCK
JTAGEN
1
JTAGEN
0
0
0
JTAGEN
0
–
TCK/ADC4
INPUT
PF0/ADC0
0
0
0
0
0
0
0
0
–
ADC0 INPUT
ATmega128
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