AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 34

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9G45-CU
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
AT91SAM9G45-CU
Manufacturer:
Atmel
Quantity:
31
Part Number:
AT91SAM9G45-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM9G45-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT91SAM9G45-CU
Quantity:
340
Part Number:
AT91SAM9G45-CU-999
Manufacturer:
Atmel
Quantity:
10 000
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
34
ARM9EJ-S Processor
AT91SAM9G45
ARM9EJ-S Operating States
Switching State
Instruction Pipelines
Memory Access
Jazelle Technology
The ARM9EJ-S processor can operate in three different states, each with a specific instruction
set:
In Jazelle state, all instruction Fetches are in words.
The operating state of the ARM9EJ-S core can be switched between:
All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or
Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle
states occurs automatically on return from the exception handler.
The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions
to the processor.
A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch,
Decode, Execute, Memory and Writeback stages.
A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch,
Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages.
The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words
must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and
bytes can be placed on any byte boundary.
Because of the nature of the pipelines, it is possible for a value to be required for use before it
has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S con-
trol logic automatically detects these cases and stalls the core or forward data.
The Jazelle technology enables direct and efficient execution of Java byte codes on ARM pro-
cessors, providing high performance for the next generation of Java-powered wireless and
embedded devices.
The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java
Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb
instructions, it executes Java byte codes. The Java byte code decoder logic implemented in
ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without
any overhead, while less frequently used byte codes are broken down into optimized sequences
of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the
application and invisible to the operating system. All existing ARM registers are re-used in
Jazelle state and all registers then have particular functions in this mode.
• ARM state: 32-bit, word-aligned ARM instructions.
• THUMB state: 16-bit, halfword-aligned Thumb instructions.
• Jazelle state: variable length, byte-aligned Jazelle instructions.
• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
• ARM state and Jazelle state using the BXJ instruction
6438F–ATARM–21-Jun-10

Related parts for AT91SAM9G45-CU