AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 768

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 36-7. Command/Response Functional Flow Diagram
Note:
36.8.2
6438F–ATARM–21-Jun-10
1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMe-
Data Transfer Operation
dia Card specification).
Check error bits in the
The High Speed MultiMedia Card allows several read/write operations (single block, multiple
blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP)
field in the HSMCI Command Register (HSMCI_CMDR).
These operations can be done using the features of the DMA Controller.
In all cases, the block length (BLKLEN field) must be defined either in the mode register
HSMCI_MR, or in the Block Register HSMCI_BLKR. This field determines the size of the data
block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
Wait for command
• Open-ended/Infinite Multiple block read (or write):
status register
ready status flag
(1)
HSMCI_ARGR = Argument
Set the command argument
HSMCI_CMDR = Command
Read response if required
Status error flags?
Set the command
Read HSMCI_SR
RETURN OK
CMDRDY
1
(1)
RETURN ERROR
Yes
0
AT91SAM9G45
(1)
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