AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 40

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4.9
9.4.10
40
AT91SAM9G45
New ARM Instruction Set
Thumb Instruction Set Overview
Table 9-2.
.
Table 9-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Mnemonic
Mnemonic
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
LDRBT
SMLAL
BLX
LDRH
LDRB
QADD
QSUB
LDRT
SWP
MCR
LDM
CDP
LDC
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
ARM Instruction Mnemonic List (Continued)
New ARM Instruction Mnemonic List
Operation
Load Half Word
Load Byte
Load Register Byte with
Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data Processing
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16 *
16 bit
Signed Multiply Accumulate Long
Signed Multiply Accumulate 32 *
16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Mnemonic
Mnemonic
STRBT
SWPB
STRH
STRB
MRRC
MCRR
STRT
MCR2
CDP2
STRD
LDRD
MRC
BKPT
STC2
LDC2
STM
STC
PLD
CLZ
Operation
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare to
load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Count Leading Zeroes
Alternative Load to Coprocessor
6438F–ATARM–21-Jun-10