ST72F63BD6U1TR STMicroelectronics, ST72F63BD6U1TR Datasheet - Page 74
ST72F63BD6U1TR
Manufacturer Part Number
ST72F63BD6U1TR
Description
MCU 8BIT LS USB 32KB FLSH 40-QFN
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BD6U1TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-QFN
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5623
497-5623-2
497-5623
ST72F63BD6U1
497-5623-2
497-5623
ST72F63BD6U1
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On-chip peripherals
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Control register 2 (CR2)
Reset value: 0000 0000 (00h)
OC1E
7
[3:2]
7
6
5
4
1
0
OC2E
OC1E output Compare 1 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1
in output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode).
Whatever the value of the OC1E bit, the output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
OC2E output Compare 2 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2
in output Compare mode). Whatever the value of the OC2E bit, the output
Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
OPM One Pulse mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on
the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal;
the length of the pulse depends on the value of OC1R register; the period
depends on the value of OC2R register.
CC[1:0] Clock Control.
The timer clock mode depends on these bits (see
If the external clock pin is not available, programming the external clock
configuration stops the counter.
IEDG2 input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
EXEDG External Clock Edge.
This bit determines which type of level transition on the external clock pin
EXTCLK will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
OPM
Doc ID 7516 Rev 8
PWM
Read/write
CC1
CC0
Table
IEDG2
24).
ST7263Bxx
EXEDG
0
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