Z8F1622AR020SG Zilog, Z8F1622AR020SG Datasheet - Page 143
Z8F1622AR020SG
Manufacturer Part Number
Z8F1622AR020SG
Description
IC ENCORE MCU FLASH 16K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F1622AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F162x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4241
Z8F1622AR020SG
Z8F1622AR020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F1622AR020SG
Manufacturer:
Zilog
Quantity:
160
Company:
Part Number:
Z8F1622AR020SG
Manufacturer:
Zilog
Quantity:
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PS019921-0308
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format PHASE Equals Zero
Figure 24
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
one. The diagram may be interpreted as either a Master or Slave timing diagram because
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
Transfer Format PHASE Equals One
Figure 25
one. Two waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for
CLKPOL set to 1.
MOSI
MISO
SCK
SCK
SS
displays the timing diagram for an SPI transfer in which PHASE is cleared to 0.
on page 130 displays the timing diagram for an SPI transfer in which PHASE is
Bit7
Bit7
Figure 24. SPI Timing When PHASE is 0
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Z8 Encore! XP
Bit2
Bit2
Bit1
Bit1
Product Specification
Serial Peripheral Interface
Bit0
Bit0
®
F64XX Series
129
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