EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 5
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued)
UP004909-0910
No
7
Issue
The UART is continually
interrupting; the user
cannot clear the interrupt.
Detailed Description
The root cause of this issue has been duplicated with certain signal
conditions after which a software instruction was executed to clear the
receive FIFO. The signals involved were from bit 0 of the ISR, and the
trigger counter with RXFIFO enabled and RXINTERRUPT disabled.
Workarounds
To prevent this error condition from occurring, you can perform one of
the following two actions:
(1)Do not enable the transmit or receive FIFO if it is not required. The
(2)If you are using either the transmit or receive FIFOs, mask off the
(3)To correct this error condition when the UART Rx interrupt occurs but
//=====================workaround=====================
/*
* Check for ‘stuck’ Fifo
*/
if( (Iir == SD_IIR_RX_INT) && ((Lsr & LSR_DR) == ) )
{
UINT32 Mcr;
/*
* To clear this condition, put the Uart in loopback
* mode and send a character
*/
Mcr = BSP_RD32 ( pUART->Base|UART_REG_MCTL );
BSP_WR32( pUart->Base|UART_REG_MCTL, Mcr | MCTL_LOOP);
BSP_WR32( pUart->Base|UART_REG_THR, ‘Z’ );
/*
* Wait for the character to hit the Rx fifo
*/
Lsr = BSP_RD32( pUart->Base | UART_REG_LSR );
while( !(Lsr & LSR_DR) )
{
Lsr = BSP_RD32( pUart->Base | UART_REG_LSR );
}
(continued)
Receive FIFO was the initial problem; however, both the TX and RX
FIFOs are affected. Set bit 0 (FIFOEN) of the UART0_FCTL
(0x0C2h) or UART1_FCTL (0x0D2h) registers to a value of zero.
following two bit locations to avoid changing the default bit value of
zero. If bit 0 (FIFOEN) of the UART0_FCTL (0x0C2h) or
UART1_FCTL (0x0D2h) registers is set to 1, then mask off bit 1
(CLRRxF) and bit 2 (CLRTxF) so that any Write accesses to the
UART0_FCTL (0x0C2h) or UART1_FCTL (0x0D2h) registers will
not alter this default zero value.
there is no Rx data detected, the user can clear the condition in
software by putting the UART in loopback mode and then
transmitting a single character. The following is an example of this
workaround:
Product Update: Errata for eZ80F92 and eZ80F93 MCUs
Page 5 of 7