ST72F321BAR9T6 STMicroelectronics, ST72F321BAR9T6 Datasheet - Page 30

MCU 8BIT 60KB FLASH/ROM 64-LQFP

ST72F321BAR9T6

Manufacturer Part Number
ST72F321BAR9T6
Description
MCU 8BIT 60KB FLASH/ROM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F321BAR9T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-5583

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0
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
Figure 18. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generate an interrupt if
the corresponding Enable Control Bit (AVDIE) is
30/187
WAIT
HALT
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
Mode
V
V
IT+(EVD)
IT-(EVD)
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
The SICSR register is frozen.
V
EVD
0
Description
INTERRUPT PROCESS
V
hyst
1
of the comparator output. This means it is generat-
ed when either one of these two events occur:
The EVD function is illustrated in
For more details, refer to the Electrical Character-
istics section.
set and the interrupt mask in the CC register is re-
set (RIM instruction).
AVD event
– V
– V
Interrupt Event
EVD
EVD
rises up to V
falls down to V
Event
AVDF
Flag
IT+(EVD)
IT-(EVD)
Control
Enable
AVDIE
Bit
INTERRUPT PROCESS
Figure
0
from
Wait
Exit
Yes
18.
from
Halt
Exit
No

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