ST72F321J9T6 STMicroelectronics, ST72F321J9T6 Datasheet - Page 191

• Manufacturer Part Number: ST72F321J9T6
• Description: MCU 8BIT 60KB FLASH 44TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20-DVP3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4844

15.4.2 LVD Startup behaviour
When the LVD is enabled, the MCU reaches its
authorized operating voltage from a reset state.
However, in some devices, the reset state is re-
leased when VDD is approximately between 0.8V
and 1.5V. As a consequence, the I/Os may toggle
when VDD is within this window.
This may be an issue especially for applications
where the MCU drives power components.
Figure 107. LVD Startup Behaviour
15.4.3 AVD not supported
On some devices with a specific V
speed the AVD may not start. As a result it cannot
generate interrupts when V
15.4.4 Internal RC oscillator operation
Internal RC oscillator operation is not supported in
ROM devices.
1.5V
0.8V
5V
V
IT+
DD
rises and falls.
Window
DD
LVD RESET
ramp up
t
15.4.5 External clock source with PLL
External clock source is not supported with the
PLL enabled.
15.4.6 Pull-up not present on PE2
Unlike ST72F321 Flash devices, ST72321 ROM
devices have no weak pull-up on port PE2.
In LQFP44 ROM devices, the PE2 pad is not con-
nected to an internal pull-up like other unbonded
pads (See note 4 under Table 2, “Device Pin De-
scription,” on page 10). It is recommended to con-
figure it as output push pull to avoid added current
consumption.
15.4.7 Read-out protection with LVD
The LVD is not supported if Readout protection is
enabled.
15.4.8 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
f
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to
25.
OSC
clock frequency in excess of the allowed
ST72321Rx ST72321ARx ST72321Jx
section 6.2 on page
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