EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet
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EZ80F91NA050SG
Specifications of EZ80F91NA050SG
EZ80F91NA050SG
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EZ80F91NA050SG Summary of contents
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... An Company ® eZ80Acclaim! Flash Microcontrollers eZ80F91 MCU Product Specification PS019215-0910 Copyright ©2010 by Zilog ® , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. eZ80, Z80, and eZ80Acclaim! are registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. ...
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Revision History Each instance in the Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Revision Date Level Section September 15 ...
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... Output Chip Selects and Wait States Flash Memory Real-Time Clock Overview Universal Asynchronous Receiver/Transmitter Infrared Encoder/Decoder Control Registers Zilog Debug Interface On-Chip Oscillators POR and VBO Electrical Characteristics Ordering Information PS019215-0910 Product Specification Description Updated for new release. Table 3: The description of the ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Zilog Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Operation of the eZ80F91 Device during ZDI Break Points . . . . . . . . . . . . . . . 238 Bus Requests During ZDI Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 ZDI Write Only Registers ...
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On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Architectural Overview Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80Acclaim! controllers. The eZ80F91 is a high-speed microcontroller with a maximum clock speed of 50 MHz and single-cycle instruction fetch. It operates in Z80 ing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80F91 makes it suitable for a variety of applications, including industrial control, embedded communication, and point-of-sale terminals ...
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IEEE 1149.1-compatible JTAG • 144-pin LQFP and BGA packages • 3 3.6 V supply voltage with 5 V tolerant inputs • Operating Temperature Range: Standard: 0 ºC to +70 ºC – Extended: –40 ºC to +105 ºC ...
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RTC_V Real-Time DD Clock and RTC_X IN 32 KHz Oscillator RTC_X OUT SCL Serial Interface SDA SCK SPI SS Serial Parallel MISO Interface MOSI WP CTS0/1 DSR0/1 UART DCD0/1 Universal DTR0/1 Asynchronous Receiver/ RI0/1 Transmitter RTS0/1 (2) ...
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Pin Description Table 1 lists the pin configuration of the eZ80F91 device in the 144-BGA package. Table 1. eZ80F91 144-BGA Pin Configuration SDA SCL PA0 PA4 V PHI PA1 PA3 PB6 PB7 ...
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Figure 2 displays the pin layout of the eZ80F91 device in the 144-pin LQFP package A10 A11 A12 A13 A14 ...
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Pin Characteristics Table 2 lists the pins and functions of the eZ80F91 MCU’s 144-pin LQFP package and 144-BGA package. Table 2. Pin Identification on the eZ80F91 Device LQFP BGA Pin No Pin No Symbol Function 1 A1 ADDR0 Address Bus ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 17 F1 ADDR12 Address Bus 18 F2 ADDR13 Address Bus 19 F3 ADDR14 Address Bus 20 F4 ADDR15 Address Bus 21 G1 ADDR16 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 39 L2 DATA0 Data Bus 40 K3 DATA1 Data Bus 41 J4 DATA2 Data Bus 42 M3 DATA3 Data Bus 43 L3 DATA4 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 53 M6 INSTRD Instruction Read Indicator 54 L6 WAIT WAIT Request Schmitt-trigger 55 K6 RESET Reset 56 J6 NMI Nonmaskable Interrupt 57 M7 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 61 M8 RTC_X Real-Time IN Clock Crystal Input 62 L8 RTC_X Real-Time OUT Clock Crystal Output 63 J7 RTC_V Real-Time DD Clock Power ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 70 M10 TDO JTAG Test Data Out 71 L10 TRST JTAG Reset 72 M11 V Ground SS 73 M12 PD0 GPIO Port D ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 75 L11 PD2 GPIO Port D RTS0 Request to Send 76 K10 PD3 GPIO Port D CTS0 Clear to Send 77 J9 PD4 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 78 K12 PD5 GPIO Port D DSR0 Data Set Ready 79 K11 PD6 GPIO Port D DCD0 Data Carrier Detect 80 H8 PD7 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 86 H11 X System Clock IN Oscillator Input 87 H10 PLL_V Power Supply Power Supply DD 89 G12 V ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 92 G9 PC2 GPIO Port C RTS1 Request to Send 93 F12 PC3 GPIO Port C CTS1 Clear to Send 94 F11 PC4 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 95 F10 PC5 GPIO Port C DSR1 Data Set Ready 96 G8 PC6 GPIO Port C DCD1 Data Carrier Detect 97 E12 PC7 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 100 E10 PB0 GPIO Port B IC0 Input Capture EC0 Event Counter Schmitt-trigger 101 D12 PB1 GPIO Port B IC1 Input Capture 102 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 103 D11 PB3 GPIO Port B SCK SPI Serial Clock 104 E9 PB4 GPIO Port B IC2 Input Capture 105 D10 PB5 GPIO ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 106 C12 PB6 GPIO Port B MISO SPI Master-In/ Slave-Out 107 C11 PB7 GPIO Port B MOSI SPI Master Out Slave In 108 ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 114 A10 PA0 GPIO Port A PWM PWM0 Output 0 OC0 Output Compare 0 115 B10 PA1 GPIO Port A PWM ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 117 B9 PA3 GPIO Port A PWM3 PWM Output 3 Output OC3 Output Compare 3 118 A9 PA4 GPIO Port A PWM0 PWM ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 120 F7 PA6 GPIO Port A PWM2 PWM Output 2 Inverted EC1 Event Counter Input 121 A8 PA7 GPIO Port A PWM3 PWM ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 127 C7 TxD2 MII Transmit Data 128 D7 TxD1 MII Transmit Data 129 A6 TxD0 MII Transmit Data 130 B6 Tx_EN MII Transmit ...
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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 137 A4 Rx_DV MII Receive Data Valid 138 E6 RxD0 MII Receive Data 139 B4 RxD1 MII Receive Data 140 D5 RxD2 MII ...
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... External Crystal Oscillator— one mode, the X is not connected. In the other mode, the X Crystals recommended by Zilog MHz range fundamental for PLL operation. For details, see 335. Real Time Clock— the on-chip 32768 Hz crystal oscillator or a 50/60 Hz power-line frequency input. While intended for timekeeping, the RTC 32 kHz oscillator is selected as an SCLK ...
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... MHz to 10 MHz generates an SCLK MHz. For more- details, see Phase-Locked Loop SCLK Source Selection Example For additional SCLK source selection examples, refer to Crystal Oscillator/Resonator Guidelines for eZ80 www.zilog.com. PS019215-0910 on page 265. ® ® and eZ80Acclaim! Devices Technical Note (TN0013) available on ...
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Register Map All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all I/O operations (ADDR[23:16] = XX). All I/O operations using ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 0026 EMAC_STAD_1 0027 EMAC_STAD_2 0028 EMAC_STAD_3 0029 EMAC_STAD_4 002A EMAC_STAD_5 002B EMAC_TPTV_L 002C EMAC_TPTV_H 002D EMAC_IPGT 002E EMAC_IPGR1 002F EMAC_IPGR2 0030 EMAC_MAXF_L 0031 EMAC_MAXF_H 0032 EMAC_AFR 0033 EMAC_HTBL_0 0034 EMAC_HTBL_1 0035 EMAC_HTBL_2 ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 003F EMAC_FIAD 0040 EMAC_PTMR 0041 EMAC_RST 0042 EMAC_TLBP_L 0043 EMAC_TLBP_H 0044 EMAC_BP_L 0045 EMAC_BP_H 0046 EMAC_BP_U 0047 EMAC_RHBP_L 0048 EMAC_RHBP_H 0049 EMAC_RRP_L 004A EMAC_RRP_H 004B EMAC_BUFSZ 004C EMAC_IEN 004D EMAC_ISTAT 004E EMAC_PRSD_L ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 0054 EMAC_TRP_H 0055 EMAC_BLKSLFT_L 0056 EMAC_BLKSLFT_H 0057 EMAC_FDATA_L 0058 EMAC_FDATA_H 0059 EMAC_FFLAGS PLL 005C PLL_DIV_L 005D PLL_DIV_H 005E PLL_CTL0 005F PLL_CTL1 Timers and PWM 0060 TMR0_CTL 0061 TMR0_IER 0062 TMR0_IIR 0063 TMR0_DR_L ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 006A TMR1_CAP_CTL 006B TMR1_CAPA_L 006C TMR1_CAPA_H 006D TMR1_CAPB_L 006E TMR1_CAPB_H 006F TMR2_CTL 0070 TMR2_IER 0071 TMR2_IIR 0072 TMR2_DR_L TMR2_RR_L 0073 TMR2_DR_H TMR2_RR_H 0074 TMR3_CTL 0075 TMR3_IER 0076 TMR3_IIR 0077 TMR3_DR_L TMR3_RR_L 0078 ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 007D PWM0R_H TMR3_CAPA_H 007E PWM1R_L TMR3_CAPB_L 007F PWM1R_H TMR3_CAPB_H 0080 PWM2R_L TMR3_OC_CTL1 0081 PWM2R_H TMR3_OC_CTL2 0082 PWM3R_L TMR3_OC0_L 0083 PWM3R_H TMR3_OC0_H 0084 PWM0F_L TMR3_OC1_L PS019215-0910 Name PWM 0 Rising-Edge Register—High Byte ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 0085 PWM0F_H TMR3_OC1_H 0086 PWM1F_L TMR3_OC2_L 0087 PWM1F_H TMR3_OC2_H 0088 PWM2F_L TMR3_OC3_L 0089 PWM2F_H TMR3_OC3_H 008A PWM3F_L 008B PWM3F_H Watchdog Timer 0093 WDT_CTL 0094 WDT_RR General-Purpose Input/Output Ports 0096 PA_DR 0097 PA_DDR ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 009A PB_DR 009B PB_DDR 009C PB_ALT1 009D PB_ALT2 009E PC_DR 009F PC_DDR 00A0 PC_ALT1 00A1 PC_ALT2 00A2 PD_DR 00A3 PD_DDR 00A4 PD_ALT1 00A5 PD_ALT2 00A6 PA_ALT0 00A7 PB_ALT0 Chip Select/Wait State Generator ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 00B4 RAM_CTL 00B5 RAM_ADDR_U 00B6 MBIST_GPR 00B7 MBIST_EMR Serial Peripheral Interface 00B8 SPI_BRG_L 00B9 SPI_BRG_H 00BA SPI_CTL 00BB SPI_SR 00BC SPI_TSR SPI_RBR Infrared Encoder/Decoder 00BF IR_CTL Universal Asynchronous Receiver/Transmitter 0 (UART0) 00C0 ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 00C7 UART0_SPR 00C8 I2C_SAR 00C9 I2C_XSAR 00CA I2C_DR 00CB I2C_CTL General-Purpose Input/Output Ports 00CE PC_ALT0 00CF PD_ALT0 00CC I2C_SR I2C_CCR 00CD I2C_SRR Universal Asynchronous Receiver/Transmitter 1 (UART1) 00D0 UART1_RBR ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic 00DB CLK_PPD1 00DC CLK_PPD2 Real-Time Clock 00E0 RTC_SEC 00E1 RTC_MIN 00E2 RTC_HRS 00E3 RTC_DOW 00E4 RTC_DOM 00E5 RTC_MON 00E6 RTC_YR 00E7 RTC_CEN 00E8 RTC_ASEC 00E9 RTC_AMIN 00EA RTC_AHRS 00EB RTC_ADOW 00EC RTC_ACTRL ...
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Table 3. Register Map (Continued) Address (hex) Mnemonic Flash Memory Control 00F5 FLASH_KEY 00F6 FLASH_DATA 00F7 FLASH_ADDR_U 00F8 FLASH_CTL 00F9 FLASH_FDIV 00FA FLASH_PROT 00FB FLASH_IRQ 00FC FLASH_PAGE 00FD FLASH_ROW 00FE FLASH_COL 00FF FLASH_PGCTL PS019215-0910 Name Flash Key Register Flash Data ...
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... Loads/unloads the I register with a 16-bit value. These new instructions are: LD I,HL (ED C7) – LD HL,I (ED D7) – For more information on the CPU, its instruction set, and eZ80 programming, refer to eZ80 CPU User Manual (UM0077), available on www.zilog.com. PS019215-0910 Product Specification 39 ® ® eZ80 ...
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PS019215-0910 Product Specification 40 ® eZ80 CPU Core ...
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Reset The Reset controller within the eZ80F91 device features a consistent reset function for all types of resets that affects the system. A system reset, referred in this document as RESET, returns the eZ80F91 to a defined state. All internal ...
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Power-On Reset A POR occurs every time the supply voltage to the part rises from below the Voltage Brownout threshold (V bandgap-referenced voltage detector sends a continuous RESET signal to the Reset con- troller until the supply voltage (V above ...
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POR V VBO Program Execution System Clock Internal RESET Signal Figure 4. Voltage Brownout Reset Operation PS019215-0910 Voltage Brown-out RESET mode T timer delay ANA Product Specification 3.3V CC Program Execution Reset ...
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PS019215-0910 Product Specification 44 Reset ...
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Low-Power Modes The eZ80F91 device provides a range of power-saving features. The highest level of power reduction is provided by SLEEP mode with all peripherals disabled, including VBO. The next level of power reduction is provided by the HALT instruction. ...
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The PC stops incrementing. The CPU is brought out of HALT mode by any of the following operations: • A nonmaskable interrupt (NMI). • A maskable interrupt. • A RESET via the external RESET pin driven Low. • A ...
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Table 4. Clock Peripheral Power-Down Register 1 Bit 7 0 Reset R/W CPU Access Note: R/W = Read/Write. Bit Position Value Description 7 1 System clock to GPIO Port D is powered down. GPIO_D_OFF Port D alternate functions do not ...
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Table 5. Clock Peripheral Power-Down Register 2 Bit 7 0 Reset R/W CPU Access Note Read Only; R/W = Read/Write. Bit Position Value Description 7 1 PHI Clock output is disabled (output is high-impedance). PHI_OFF 0 PHI Clock ...
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General-Purpose Input/Output The eZ80F91 device features 32 General-Purpose Input/Output (GPIO) pins. The GPIO pins are assembled as four 8-bit ports—Port A, Port B, Port C, and Port D. All port signals are configured as either inputs or outputs. In addition, ...
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Table 6. GPIO Mode Selection GPIO Px_ALT2 Px_ALT1 Px_DDR Mode Bits7:0 Bits7:0 Bits7 ...
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Writing 0 to the Port x Data register outputs a Low at the pin. Writing 1 to the Port x Data register results in high-impedance output. GPIO Mode ...
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GPIO Mode 8—Level Sensitive Interrupt The port pin is configured for level-sensitive interrupt mode. The value in the Port x Data register determines if a low or high-level causes an interrupt request. An interrupt request is generated when the level ...
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Simplified GPIO Port Block Diagram for Modes 2, 6, 7(input), 8, and 9 Mode 2 Mode 6 Mode 8 Mode 9 Mode 7(Input) * Reading from the Px_DR returns the value stored in this register Figure 5. GPIO Port Pin ...
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GPIO Interrupts Each port pin is used as an interrupt source. Interrupts are either level- or edge-triggered. Level-Triggered Interrupts When the port is configured for level-triggered interrupts (mode 8), the corresponding port pin is open-drain. An interrupt request is generated ...
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Edge triggered interrupts are cleared by writing 1 to the corresponding bit of the Px_ALT0 register. For example, if PD4 has been set up to generate an edge triggered interrupt, the interrupt is cleared by writing Px_ALT0[4]. ...
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Port x Alternate Register 0 The Port x Alternate register 0 is used to clear edge triggered interrupts edge triggered interrupt occurs, writing 1 to the corresponding bit of this register will clear it. Table 9. Port x ...
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Interrupt Controller The interrupt controller on the eZ80F91 device routes the interrupt request signals from the internal peripherals, external devices (via the internal port I/O), and the nonmaskable interrupt (NMI) pin to the CPU. Maskable Interrupts On the eZ80F91 device, ...
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Table 12. Interrupt Vector Sources by Priority (Continued) Priority Vector Source 11 06Ch RTC 12 070h UART 0 13 074h UART 078h I 15 07Ch SPI 16 080h Port 084h Port ...
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Setting the LSB of the I register produces no effect on the interrupt vector address. Table 13. Vectored Interrupt Operation Memory ADL MADL Mode Bit Bit Operation ® Z80 Mode 0 0 Read the LSB of the interrupt vector ...
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Table 13. Vectored Interrupt Operation (Continued) Memory ADL MADL Mode Bit Bit Operation ADL Mode 1 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [8:0], by the interrupting peripheral. • IEF1 • ...
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Table 14. Interrupt Priority Registers = 0013h, INT_P4 = 0014h, INT_P5 = 0015h) Bit 7 0 INT_P0 Reset 0 INT_P1 Reset 0 INT_P2 Reset 0 INT_P3 Reset 0 INT_P4 Reset 0 INT_P5 Reset R/W CPU Access Note Undefined; ...
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The Interrupt Vector Priority Control bits are listed in Table 15. Interrupt Vector Priority Control Bits Priority Control Bit Vector INT_P0[0] 040h INT_P0[1] 044h INT_P0[2] 048h INT_P0[3] 04Ch INT_P0[4] 050h INT_P0[5] 054h INT_P0[6] 058h INT_P0[7] 05Ch INT_P1[0] 060h INT_P1[1] 064h ...
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Table 16 lists the maskable interrupts (RTC) as elevated to priority Level 1. ten maskable interrupts. Table 16. Example: Maskable Interrupt Priority Priority Register Setting INT_P0 02h INT_P1 08h INT_P2 02h INT_P3 00h INT_P4 00h INT_P5 00h Table 17. Example: ...
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GPIO Port Interrupts All interrupts are latched. In effect, an interrupt is held even if the interrupt occurs while another interrupt is being serviced and interrupts are disabled the interrupt lower priority. However, before the ...
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Chip Selects and Wait States The eZ80F91 generates four chip selects for external devices. Each chip select is pro- grammed to access either the memory space or the I/O space. The memory chip selects are individually programmed ...
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If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a particular chip select is valid for a single 64 KB page. Memory Chip Select Priority A lower-numbered chip select is granted priority over ...
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CS3_UBR = FFh CS3_LBR = D0h CS2_UBR = CFh CS2_LBR = A0h CS1_UBR = 9Fh CS0_UBR = 7Fh CS0_LBR = CS1_LBR = 00h Table 18. Example: Register Values for Figure 7 Memory Chip Select Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO ...
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Input/Output Chip Select Operation I/O chip selects will be active only when the CPU is performing I/O instructions. Because the I/O space is separate from the memory space in the eZ80F91 device, a conflict between I/O and memory addresses never ...
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WAIT Input Signal Similar to the programmable wait states, an external peripheral drives the WAIT input pin to force the CPU to provide additional clock cycles to complete its Read or Write opera- tion. Driving the WAIT pin Low stalls ...
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SCLK ADDR[23:0] DATA[7:0] (output) CSx MREQ RD INSTRD Figure 9. Example: Wait State Read Operation Chip Selects During Bus Request/Bus Acknowledge Cycles When the CPU relinquishes the address bus to an external peripheral in response to an external bus request ...
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CPU system clock cycles per bus mode state is also independently programmable. For Intel bus mode, multiplexed address and data are selected in which both the lower byte of the address and the data byte use the data bus, DATA[7:0]. ...
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Z80 bus mode Read and Write timing is displayed in 73. The Z80 bus mode states are configured for CPU system clock cycles. In the figures, each Z80 bus mode state is two CPU system clock ...
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System Clock ADDR[23:0] DATA[7:0] CSx RD WAIT WR MREQ or IORQ Figure 11. Example: Z80 Intel Bus Mode Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four-state memory transfer similar to that ...
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Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Figure 12. Intel Bus Mode Signal and Pin Mapping Intel™ Bus Mode—Separate Address and Data Buses During Read operations with separate address and data buses, the Intel ...
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Table 21. Intel Bus Mode Read States—Separate Address and Data Buses (Continued) STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior to ...
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System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or IORQ Figure 13. Example: Intel Bus Mode Read Timing—Separate Address and Data Buses PS019215-0910 WAIT eZ80F91 MCU Product Specification 76 T4 Chip Selects and Wait ...
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System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ Figure 14. Example: Intel Bus Mode Write Timing—Separate Address and Data Buses PS019215-0910 WAIT eZ80F91 MCU Product Specification 77 T4 Chip Selects and Wait ...
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Intel™ Bus Mode—Multiplexed Address and Data Bus During Read operations with multiplexed address and data, the Intel™ bus mode employs four states—T1, T2, T3, and T4 as listed in Table 23. Intel Bus Mode Read States—Multiplexed Address and Data Bus ...
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System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or IORQ Figure 15. Example: Intel Bus Mode Read Timing—Multiplexed Address and Data Bus PS019215-0910 WAIT eZ80F91 MCU Product Specification 79 T4 Chip Selects and Wait ...
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System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ Figure 16. Example: Intel Bus Mode Write Timing—Multiplexed Address and Data Bus Motorola Bus Mode Chip selects configured for Motorola bus mode modify the CPU bus signals to ...
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Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Figure 17. Motorola Bus Mode Signal and Pin Mapping During Write operations, the Motorola bus mode employs eight states—S0, S1, S2, S3, S4, S5, S6, and S7 ...
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Table 25. Motorola Bus Mode Read States (Continued) STATE S6 During state S6, data from the external peripheral device is driven onto the data bus. STATE S7 On the rising edge of the clock entering state S7, the CPU latches ...
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S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 18. Example: Motorola Bus Mode Read Timing PS019215-0910 eZ80F91 MCU Product Specification Chip Selects and Wait States 83 ...
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S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 19. Example: Motorola Bus Mode Write Timing Switching Between Bus Modes When switching bus modes between Intel™ to Motorola, Motorola to Intel™, eZ80 Motorola, or eZ80 ...
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Chip Select Registers Chip Select x Lower Bound Register For Memory chip selects, the chip select x Lower Bound register (see the lower bound of the address range for which the corresponding Memory chip select (if enabled) is active. For ...
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Chip Select x Upper Bound Register For Memory chip selects, the Chip Select x Upper Bound registers, listed in defines the upper bound of the address range for which the corresponding Chip Select (if enabled) are active. For I/O chip ...
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Chip Select x Control Register The Chip Select x Control register (see type of chip select, and sets the number of wait states. The reset state for the Chip Select 0 Control register is . 00h Table 29. Chip Select ...
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Chip Select x Bus Mode Control Register The Chip Select Bus Mode register (see ® Z80 , Intel™, or Motorola bus modes. Changing the bus mode allows the eZ80F91 device to interface to peripherals based on the Z80, Intel™, or ...
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Bit Position Value Description [3:0] 0000 Not valid. BUS_CYCLE 0001 Each bus mode state is 1 eZ80 0010 Each bus mode state is 2 eZ80 clock cycles in duration. 0011 Each bus mode state is 3 eZ80 clock cycles ...
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Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles Pin Symbol ADDR23..ADDR0 CS0 CS1 CS2 CS3 DATA7..0 IORQ MREQ RD WR INSTRD Normal bus operation of the eZ80F91 device using CS0 to communicate to an external peripheral is displayed in ...
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External Master MREQ Figure 20. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation External Master MREQ Figure 21. Memory Interface Bus Operation During Bus Acknowledge Cycles During bus acknowledge cycles, the Memory and I/O chip select logic is ...
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The following chip select features are not available during bus acknowledge cycles: • The chip select logic does not insert wait states during bus acknowledge cycles regard- less of the WAIT configuration for the decoded chip select. • The bus ...
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Random Access Memory The eZ80F91 device features 8 KB (8192 bytes) of single-port data Random Access Memory (RAM) for general-purpose use and RAM for the EMAC. RAM is enabled or disabled, and it is relocated to the ...
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On-chip RAM is not accessi- ble to external devices during bus acknowledge cycles. RAM Control Registers RAM Control Register Internal general-purpose RAM is disabled by clearing the GPRAM_EN bit. The ...
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RAM Address Upper Byte Register The RAM_ADDR_U register defines the upper byte of the address for on-chip RAM. If enabled, RAM addresses assume priority over all Chip Selects. The external Chip Select signals are not asserted if the corresponding ...
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MBIST Control There are two Memory Built-In Self-Test (MBIST) controllers for the RAM blocks on the eZ80F91. MBIST_GPR is for General-Purpose RAM and MBIST_EMR is for EMAC RAM. Writing MBIST_ON starts the MBIST testing. Writing a 0 ...
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Flash Memory The eZ80F91 device features 256 KB (262,144 bytes) of non-volatile Flash memory with Read/Write/Erase capability. The main Flash memory array is arranged in 128 pages with 8 rows per page and 256 bytes per row. In addition to ...
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Flash Memory Overview The eZ80F91 device includes a Flash memory controller that automatically converts standard CPU Read and Write cycles to the specific protocol required for the Flash memory array. As such, standard memory Read and Write instructions access ...
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Memory Read A memory Read operation uses the address bus and data bus of the eZ80F91 device to read a single data byte from Flash memory. This Read operation is similar to reads from RAM. To perform Flash memory reads, ...
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Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). A typical sequence that performs a single-byte I/O Write is shown below. Because the Write is self-timed, ing or interrupts. 1. Write the FLASH_PAGE, FLASH_ROW, and ...
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Otherwise, the burden is on software to ensure that the 31 ms maximum cumulative programming time between erases is not exceeded for a row. Memory Write A single-byte memory Write operation uses the address bus and ...
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Information Page Characteristics As noted earlier, the information page is not accessible using memory access instructions and must be accessed via the FLASH_DATA I/O register. The Flash Page Select Register contains a bit which selects the information page for I/O ...
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Flash Data Register The Flash Data register stores the data values to be programmed into Flash memory via I/O Write operations. An I/O read of the Flash Data register returns data from Flash memory. The Flash memory address used ...
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Flash Address Upper Byte Register The FLASH_ADDR_U register defines the upper 6 bits of the Flash memory address space. Changing the value of FLASH_ADDR_U allows on-chip 256 KB Flash memory to be mapped to any location within the 16 MB ...
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Flash Control Register The Flash Control register enables or disables memory access to Flash memory. I/O access to the Flash control registers and to Flash memory is still possible while Flash memory space access is disabled. The minimum access time ...
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Flash Frequency Divider Register The 8-bit frequency divider allows the programming of Flash memory over a range of system clock frequencies. Flash is programmed with system clock frequencies ranging from 154 kHz to 50 MHz. The Flash controller requires ...
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Flash Write/Erase Protection Register The Flash Write/Erase Protection register prevents accidental Write or Erase operations. The protection is limited to a resolution of eight 32 KB blocks. Setting a bit to 1 protects that 32 KB block of Flash memory ...
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Bit Position [1] BLK1_PROT [0] BLK0_PROT Note: The lower 32 KB block (00000h to 07FFFh—BLK0) is called the Boot block and is protected using the external WP pin. Flash Interrupt Control Register There are two sources of interrupts from the ...
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Table 42. Flash Interrupt Control Register Bit Reset CPU Access Note: R/W = Read/Write Read Only. Read resets bits [5] and [3:0]. Bit Position [7] DONE_IEN [6] ERR_IEN [5] DONE [4] [3] WR_VIO [2] RP_TMO [1] PG_VIO [0] ...
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FLASH_DATA register causes an autoincrement of the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). See Table 43. Flash Page Select Register Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position ...
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Flash Row Select Register The Flash Row Select Register is a 3-bit value used to define one of the 8 rows of Flash on a single page. This register is used for all I/O access to Flash memory. In addition, ...
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Flash Column Select Register The Flash Column Select Register is an 8-bit value used to define one of the 256 bytes of Flash memory contained in a single row. This register is used for all I/O access to Flash memory. ...
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Table 46. Flash Program Control Register Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position [7:3] [2] ROW_PGM [1] PG_ERASE [0] MASS_ERASE PS019215-0910 (FLASH_PGCTL = 00FFh ...
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PS019215-0910 eZ80F91 MCU Product Specification 114 Flash Memory ...
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Watchdog Timer The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which places the CPU into unsuitable operating states. The eZ80F91 WDT features: • Four programmable time-out ranges (depending on the WDT ...
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Watchdog Timer Operation Enabling and Disabling the Watchdog Timer The WDT is disabled on a RESET. To enable the WDT, the application program must set WDT_EN, which is bit 7 of the WDT_CTL register. After WDT_EN is set, no Writes ...
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If the NMI_OUT bit in the WDT_CTL register is set to 1, then on time-out, the WDT asserts an NMI for CPU processing. The NMI_FLAG bit is polled by the CPU to deter- mine the source of the NMI event. ...
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Bit Position [3:2] WDT_CLK [1:0] WDT_PERIOD Note: When the WDT is enabled, no Writes are allowed to the WDT_CTL register. PS019215-0910 Value Description 00 WDT clock source is system clock. 01 WDT clock source is Real-Time Clock source (32 kHz ...
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Watchdog Timer Reset Register The WDT Reset register (see when an value followed by a A5h occurs between the writing of does not occur prior to completion. Any value other than register after the the timer to be reset. Table ...
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PS019215-0910 eZ80F91 MCU Product Specification 120 Watchdog Timer ...
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Programmable Reload Timers The eZ80F91 device features four programmable reload timers. The core of each timer is a 16-bit downcounter. In addition, each timer features a selectable clock source, adjustable prescaling and operates in either SINGLE PASS or CONTINUOUS mode. ...
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Basic Timer Operation Basic timer operation is controlled by a timer control register and a programmable reload value. The CPU uses the control register to setup the prescaling, the input clock source, the end-of-count behavior, and to start the timer. ...
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Minimum time-out duration is four times longer than the input clock period and is gener- ated by setting the clock divider ratio to 1:4 and the reload value to time-out duration is 2 erated by setting the clock divider ratio ...
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TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge and the timer continues to count until disabled. An example of the timer operating in CONTINUOUS mode is displayed in Table 51. System Clock Clock Enable TMR3_CTL Write (Timer ...
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... The response of the CPU to this interrupt service request is a function of the CPU’s inter- rupt enable flag, IEF1. For more information about this flag, refer to the eZ80 Manual (UM0077) available on www.zilog.com. Timer Input Source Selection Timers 0–3 features programmable input source selection. By default, the input is taken from the eZ80F91’ ...
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Break Point Halting System Clock Clock Enable TMR3_CTL Write (Timer Enable) T3 Count 0 Timer Out (internal) Timer Out (at pad) Figure 29. Example: PRT Timer Output Operation Table 52. Example: PRT Timer Out Parameters Parameter Timer Enable Reload Prescaler ...
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Timer 0 No special functions – • Timer 1 One event counter (EC0) – Two input captures (IC0 and IC1) – • Timer 2 One event counter (EC1) – • Timer 3 Two input captures (IC2 and IC3) – ...
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RTC Oscillator Input When the timer clock source is the Real-Time Clock (RTC) signal, the timer functions just as it does in EVENT COUNT mode, except that it samples the internal RTC clock rather than the ECx pin. Input Capture ...
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Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUTPUT COMPARE events and sets output 0 as the master result, outputs 1, 2, and 3 are caused to disregard output-specific configuration and comparison values and instead mimic the current settings ...
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Timer Registers The CPU monitors and controls the timer using seven 8-bit registers. These registers are the control register, the interrupt identification register, the interrupt enable register and the reload register pair (High and Low byte). There are also a ...
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TMR3_OC_CTL2 – • Compare Value Registers TMR3_OC3_H – TMR3_OC3_L – TMR3_OC2_H – TMR3_OC2_L – TMR3_OC1_H – TMR3_OC1_L – TMR3_OC0_H – TMR3_OC0_L – Multiple PWM mode uses the following 19 registers: • PWM Control Registers TMR3_PWM_CTL1 – TMR3_PWM_CTL2 – TMR3_PWM_CTL3 – ...
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Timer Control Register The Timer x Control Register (see enabling the timer, selecting the clock source, selecting the clock divider, selecting between CONTINUOUS and SINGLEPASS modes, and enabling the auto-reload feature. Table 54. Timer Control Register TMR2_CTL = 006Fh, ...
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RLD 1 0 0 TIM_EN 1 Timer Interrupt Enable Register The Timer x Interrupt Enable Register (see operations. Only bits related to functions present in a given timer are active. Table 55. Timer Interrupt Enable TMR2_IER = 0070h, ...
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IRQ_ICB_EN 1 IRQ_ICA_EN 0 IRQ_EOC_EN PS019215-0910 Interrupt requests for ICx are disabled (valid only in INPUT CAPTURE mode). 0 Timer 1: the capture pin is IC1. Timer 3: the capture pin is IC3. Interrupt requests for ICx are enabled ...
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Timer Interrupt Identification Register The TImer x Interrupt Identification Register (see that the CPU determines the cause of a timer interrupt. This register is cleared by a CPU Read. Table 56. Timer Interrupt Identification Register 0067h, TMR2_IIR = 0071h, TMR3_IIR ...
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Timer Data Register—Low Byte The Timer x Data Register—Low Byte returns the Low byte of the current count value of the selected timer. The Timer Data Register—Low Byte (see timer is in operation. Reading the current count value does not ...
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Timer Data Register—High Byte The Timer x Data Register—High Byte returns the High byte of the count value of the selected timer as it existed at the time that the Low byte was read. The Timer Data Register—High Byte ...
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Timer Reload Register—Low Byte The Timer x Reload Register—Low Byte (see (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer on end-of-count. When the reload bit (TMRx_CTL[RLD]) is set to ...
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Timer Reload Register—High Byte The Timer x Reload Register—High Byte (see (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer upon end-of-count. When the reload bit (TMRx_CTL[RLD]) is set to ...
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CAP_EDGE_B [1:0] CAP_EDGE_A Timer Input Capture Value A Register—Low Byte The Timer x Input Capture Value A Register—Low Byte (see byte of the capture value for external input A. For Timer 1, the external input is IC0. For Timer ...
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Timer Input Capture Value A Register—High Byte The Timer x Input Capture Value A Register—High Byte (see byte of the capture value for external input A. For Timer 1, the external input is IC0. For Timer IC2. ...
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Timer Input Capture Value B Register—High Byte The Timer x Input Capture Value B Register—High Byte (see byte of the capture value for external input B. For Timer 1, the external input is IC0. For Timer IC3. ...
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OC1_INIT 2 OC0_INIT 1 MAST_MODE 0 OC_EN Timer Output Compare Control Register 2 The Timer3 Output Compare Control Register 2 (see that occurs on the output compare pins when a timer compare happens. Table 67. Timer Output Compare Control ...
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OC1_MODE [1:0] OC0_MODE Timer Output Compare Value Register—Low Byte The Timer3 Output Compare x Value Register—Low Byte (see byte of the compare value for OC0–OC3. Table 68. Compare Value Register—Low Byte TMR3_OC1_L = 0084h, TMR3_OC2_L = 0086h, TMR3_OC3_L = ...
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Timer Output Compare Value Register—High Byte The Timer3 Output Compare x Value Register—High Byte (see byte of the compare value for OC0–OC3. Table 69. Compare Value Register—High Byte TMR3_OC1_H = 0085h, TMR3_OC2_H = 0087h, TMR3_OC3_H = 0089h) Bit Reset CPU ...
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Timer 3 16-Bit Binary Downcounter Timer 3 Count Value Clock Input Figure 30. Multi-PWM Simplified Block Diagram Setting TMR3_PWM_CTL1[MPWM_EN enables Multi-PWM mode. The TMR3_PWM_CTL1 register bits enable the four individual PWM generators by adjusting settings according to the ...
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The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally enabled by setting TMR3_PWM_CTL1[PAIR_EN The individual PWM generators must be enabled for the associated inverted PWM signals to be output. For each of the 4 PWM generators, ...
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Table 71. Example: Multi-PWM Addressing Parameter Timer Reload Value PWM0 rising edge PWM0 falling edge PWM1 rising edge PWM1 falling edge PWM enable PWM0 enable PWM1 enable Multi-PWM enable Prescaler Divider = 4 PWM nonoverlapping delay = 0 TMR3_PWM_CTL2[PWM_DLY] PWM ...
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The PWM generator holds the current output state until the counter reloads and cycles through to the appropriate edge transition value again. In effect, an entire cycle of the ...
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PWM0 Signal PADR0 PWM0 Signal PADR4 Figure 33. PWM AND/OR Gating Functional Diagram If you enable the OR function on all PWM outputs and PADR0 is set to 1, then the PWM0 output on PA0 is forced High. Similarly, if ...
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The PWM delay feature is displayed in Figure 34 with associated addressing listed in Note: ...
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Multi-PWM Power-Trip Mode When enabled, the Multi-PWM power-trip feature forces the enabled PWM outputs to a predetermined state when an interrupt is generated from an external source via IC0, IC1, IC2, or IC3. One or multiple external interrupt sources are ...
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Multi-PWM Control Registers Pulse-Width Modulation Control Register 1 The PWM Control Register 1 (see Table 73. PWM Control Register 1 Bit Reset CPU Access Note: R/W = Read/Write. Bit Position 7 PAIR_EN 6 PT_EN 5 MM_EN 4 pwm3_en 3 pwm2_en ...
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Pulse-Width Modulation Control Register 2 The PWM Control Register 2 (see and edge delay functions. Table 74. PWM Control Register 2 Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:6] AON_EN [5:4] AO_EN PS019215-0910 Table 74) controls pulse-width ...
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PWM_DLY PS019215-0910 No delay between falling edge of PWM (PWM) and rising 0000 edge of PWM (PWM) Delay of 1 SCLK periods between falling edge of PWM 0001 (PWM) and rising edge of PWM (PWM) Delay of 2 SCLK ...
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Pulse-Width Modulation Control Register 3 The PWM Control Register 3 (see functionality. Table 75. PWM Control Register 3 Bit Reset CPU Access Note: R/W = Read/Write Read only. Bit Position Value 0 7 PT_IC3_EN 1 0 6 PT_IC2_EN ...
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Pulse-Width Modulation Rising Edge—Low Byte A parallel 16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs when software initiates a Write to TMR3_PWMxR_L. The register is listed in Table 76. Table 76. PWMx Rising-Edge Register—Low Byte TMR3_PWM1R_L = 007Eh, TMR3_PWM2R_L = 0080h, ...
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Pulse-Width Modulation Falling Edge—Low Byte A parallel 16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs when software initiates a Write to TMR3_PWMxF_L. The register is listed in Table 78. PWMx Falling-Edge Register—Low Byte TMR3_PWM1F_L = 0086h, TMR3_PWM2F_L = 0088h, TMR3_PWM3F_L = 008Ah) ...
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Real-Time Clock Real-Time Clock Overview The Real-Time Clock (RTC) maintains time by keeping count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour format. The format for all count and alarm registers is ...
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Real-Time Clock Alarm The clock is programmed to generate an alarm condition when the current count matches the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and day-of-the-week. Each alarm is independently enabled. To generate an alarm ...
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Write values to the RTC count registers to set the current time • Write values to the RTC alarm registers to set the appropriate alarm conditions • Write to RTC_CTRL to clear RTC_UNLOCK; clearing the RTC_UNLOCK bit resets and ...
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Real-Time Clock Minutes Register This register contains the current minutes count. The value in the RTC_MIN register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) ...
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Real-Time Clock Hours Register This register contains the current hours count. The value in the RTC_HRS register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) ...
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Real-Time Clock Day-of-the-Week Register This register contains the current day-of-the-week count. The RTC_DOW register begins counting at 01h current setting of BCD_EN determines whether the value in this register is binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). ...
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Real-Time Clock Day-of-the-Month Register This register contains the current day-of-the-month count. The RTC_DOM register begins counting at 01h current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). ...
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Real-Time Clock Month Register This register contains the current month count. The RTC_MON register begins counting at . The value in the RTC_MON register is unchanged by a RESET. The current setting 01h of BCD_EN determines whether the values in ...
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Real-Time Clock Year Register This register contains the current year count. The value in the RTC_YR register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or ...
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Real-Time Clock Century Register This register contains the current century count. The value in the RTC_CEN register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or ...
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Real-Time Clock Alarm Seconds Register This register contains the alarm seconds value. The value in the RTC_ASEC register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) ...
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Real-Time Clock Alarm Minutes Register This register contains the alarm minutes value. The value in the RTC_AMIN register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = ...
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Real-Time Clock Alarm Hours Register This register contains the alarm hours value. The value in the RTC_AHRS register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = ...
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Real-Time Clock Alarm Day-of-the-Week Register This register contains the alarm day-of-the-week value. The value in the RTC_ADOW register is unchanged by a RESET. The current setting of BCD_EN determines whether the value in this register is binary (BCD_EN = 0) ...
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Real-Time Clock Alarm Control Register This register contains control bits for the Real-Time Clock. The RTC_ACTRL register is cleared by a RESET. See Table 92. Real-Time Clock Alarm Control Register Bit 7 0 Reset R CPU Access Note ...
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If the power-line frequency option is selected, the prescale value is set by the FREQ_SEL bit, and the 32 kHz oscillator is disabled. See Table 93. Real-Time Clock Control Register Bit 7 X Reset R CPU Access Note: X ...
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Universal Asynchronous Receiver/Transmitter The UART module implements all of the logic required to support the asynchronous com- munications protocol. The module also implements two separate 16-byte-deep FIFOs for both transmission and reception. A block diagram of the UART is ...
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UART Functional Description The UART Baud Rate Generator (BRG) creates the clock for the serial transmit and receive functions. The UART module supports all of the various options in the asynchro- nous transmission and reception protocol including: • ...
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UARTx_LCTL register. When enabled, an interrupt is generated after the final protocol bit is transmitted which the CPU resets by loading data into the UARTx_THR register. The TxD output is set ...
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UART Interrupts There are six different sources of interrupts from the UART. The six sources of interrupts are: • Transmitter (two different interrupts) • Receiver (three different interrupts) • Modem status UART Transmitter Interrupt A Transmitter Hold Register Empty interrupt ...
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An interrupt due to one of the above conditions is cleared when the UARTx_LSR register is read. In case of FIFO mode, a line status interrupt is generated only after the received byte with an error reaches the top of ...
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When the application makes this determination, it writes the transmit data bytes to the UARTx_THR register. The number of bytes that the application writes depends on whether or not the FIFO is enabled. If the FIFO is enabled, ...
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UARTx_LSR register before reading the UARTx_RBR register to determine that there is no error in the received data. To control and check modem status, the application sets up the modem by writing to the UARTx_MCTL register and reading the UARTx_MSR ...
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BRG Control Registers UART Baud Rate Generator Register—Low and High Bytes The registers hold the Low and High bytes of the 16-bit divisor count loaded by the CPU for UART baud rate generation. The 16-bit clock divisor value is returned ...
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Table 95. UART Baud Rate Generator Register—High Bytes UART1_BRG_H = 00D1h) Bit Reset R/W CPU Access Note Read only; R/W = Read/Write. Bit Position Value [7:0] 00h–FFh UART_BRG_H UART Registers After a system reset, all UART registers ...
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Table 96. UART Transmit Holding Registers Bit 7 X Reset W CPU Access Note Write Only. Bit Position Value Description [7:0] 00h–FFh Transmit data byte UART Receive Buffer Register The bits in this register ...
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Table 98. UART Interrupt Enable Registers Bit Reset R/W CPU Access Note: R/W = Read/Write. Bit Position Value Description [7:5] 000 Reserved. 0 Transmission complete interrupt is disabled. 4 Transmission complete interrupt is generated when both the transmit hold ...
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UART Interrupt Identification Register The Read Only UARTx_IIR register allows you to check whether the FIFO is enabled and the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL registers. See Table 99 Table 99. UART ...
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UART FIFO Control Register This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR registers. See Table Table 101. UART FIFO Control ...
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Bit Position Value Description 0 FIFOs are not used. Receive and transmit FIFOs are used–You must clear the 0 FIFO logic using bits 1 and 2. First enable the FIFOs by setting FIFOEN 1 bit then ...
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Bit Position Value Description Even Parity Select. Use odd parity for transmit and receive. The total number of 1 bits in the transmit 0 data plus parity bit is odd. Used as SPACE bit in Multidrop Mode. See page ...
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Table 104. Parity Select Definition for Multidrop Communications Multidrop Mode Note: *In Multidrop Mode, EPS resets to 0 after the first character is sent. UART Modem Control Register This register is used to control and check ...
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Bit Position Value Description No function in normal operation. 3 0–1 In LOOP BACK mode, this bit is connected to the DCD bit in the UART Status OUT2 Register. No function in normal operation. 2 0–1 In LOOP BACK ...