EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 322
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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- Download datasheet (3Mb)
Table 198. EMAC MII Management Register (EMAC_MIIMGT = 003Bh)
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
LCTLD
6
RSTAT
5
SCINC
4
SCAN
3
SPRE
EMAC MII Management Register
The EMAC MII Management Register is used to control the external PHY attached to the
MII. See
Value
1
0
1
0
1
0
1
0
1
0
Table
Description
Rising edge causes the CTLD control data to be transmitted to
external PHY if MII is not busy. This bit is self clearing.
No operation.
Rising edge causes status to be read from external PHY via
PRSD[15:0] bus if MII is not busy. This bit is self clearing.
No operation.
Scan PHY address increments upon SCAN cycle. The SCAN
bit must also be set for the PHY address to increment after
each scan. The scanning starts at the EMAC_FIAD and
increments up to 1Fh. It then returns to the EMAC_FIAD
address.
Normal operation.
Perform continuous Read cycles via MII management. While in
SCAN mode, the EMAC_ISTAT[MGTDONE] bit is set when the
current PHY Read has completed. At this time, the
EMAC_PRSD register holds the Read data and the
EMAC_MIISTAT[4:0] holds the address of the PHY for which
the EMAC_PRSD data pertains.
Normal operation.
Suppress the MDO preamble. MDO is management data
output, an internal signal driven from the MDIO pin.
Normal preamble.
R/W
7
0
198.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
313
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