EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 200
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 106. UART Line Status Registers
PS019215-0910
Bit
Position
3
OUT2
2
OUT1
1
RTS
0
DTR
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
ERR
6
TEMT
UART Line Status Register
This register is used to show the status of UART interrupts and registers. See
Value
0–1
0–1
0–1
0–1
Value
0
1
0
1
Description
No function in normal operation.
In LOOP BACK mode, this bit is connected to the DCD bit in the UART Status
Register.
No function in normal operation.
In LOOP BACK mode, this bit is connected to the RI bit in the UART Status
Register.
Request to Send.
In normal operation, the RTS output port is the inverse of this bit. In LOOP
BACK mode, this bit is connected to the CTS bit in the UART Status Register.
Data Terminal Ready.
In normal operation, the DTR output port is the inverse of this bit. In LOOP
BACK mode, this bit is connected to the DSR bit in the UART Status Register.
Description
Always 0 when operating in with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register is
read and there are no more bytes with error status in the FIFO.
Error detected in the FIFO. There is at least 1 parity, framing or
break indication error in the FIFO.
Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
R
7
0
R
6
1
R
5
1
(UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
R
4
0
R
3
0
Universal Asynchronous Receiver/Transmitter
R
2
0
R
1
0
Product Specification
R
0
0
eZ80F91 MCU
Table
106.
191
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