MC908JL16CFJER Freescale Semiconductor, MC908JL16CFJER Datasheet - Page 114

• Manufacturer Part Number: MC908JL16CFJER
• Description: IC MCU 8BIT 16K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CFJER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: MC908JL16CFJERTR

Multi-Master IIC Interface (MMIIC)
8.4.9 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may
hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and
forces the master clock into wait states until the slave releases the SCL line.
8.4.10 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
8.4.11 Modes of Operation
The basic mode of operation for the IIC module is normal mode. When the MCU issues a STOP
instruction, the IIC module will power down while the STOP mode signal is active. The STOP instruction
does not affect IIC register states.
8.5 Interrupts
The following MMIIC source can generate interrupt requests:
8.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.6.1 Wait Mode
The MMIC module remains active in wait mode.
8.6.2 Stop Mode
The MMIIC module remains active in stop mode.
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Multi-Master IIC Arbitration Lost Interrupt Flag (MMALIF) — MMALIF is set when software attempt
to set MMAST but the MMBB has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a “1” to SDA line but detected a “0” from SDA line in master mode – an
arbitration loss.
Multi-Master IIC Receive Interrupt Flag (MMRXIF) — MMRXIF is set after the data receive register
(MMDRR) is loaded with a new received data. Once the MMDRR is loaded with received data, no
more received data can be loaded to the MMDRR register until the CPU reads the data from the
MMDRR to clear MMRXBF flag.
Multi-Master IIC Transmit Interrupt Flag (MMTXIF) — MMTXIF is set when data in the data transmit
register (MMDTR) is downloaded to the output circuit, and that new data can be written to the
MMDTR.
MC68HC908JL16 Data Sheet, Rev. 1.1
Freescale Semiconductor