MC908JL16CFJER Freescale Semiconductor, MC908JL16CFJER Datasheet - Page 126

IC MCU 8BIT 16K FLASH 32-LQFP

MC908JL16CFJER

Manufacturer Part Number
MC908JL16CFJER
Description
IC MCU 8BIT 16K FLASH 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908JL16CFJER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
26
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
For Use With
DEMO908JL16E - BOARD DEMO FOR MC908JL16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
MC908JL16CFJERTR

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Analog-to-Digital Converter (ADC)
A blocking mechanism prevents a new result from overwriting previous data in ADRH and ADRL if the
previous data is in the process of being read while in 10-bit mode (ADRH has been read but ADRL has
not). In this case the data transfer is blocked, COCO is not set, and the new result is lost. When a data
transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous
conversions enabled). If single conversions are enabled, this could result in several discarded
conversions and excess power consumption. To avoid this issue, the data registers must not be read after
initiating a single conversion until the conversion completes.
9.3.3.3 Aborting Conversions
Any conversion in progress will be aborted when:
When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADRH and ADRL return to their reset states.
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
9.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in
126
A write to ADCSC occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
A write to ADCLK occurs.
The MCU is reset.
The MCU enters stop mode with ACLK not enabled.
8-Bit Mode (short sample — ADLSMP = 0):
8-Bit Mode (long sample — ADLSMP = 1):
10-Bit Mode (short sample — ADLSMP = 0):
10-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Table 9-1. Total Conversion Time versus Control Conditions
Conversion Mode
Bus
Bus
Bus
Bus
≥ f
≥ f
≥ f
≥ f
MC68HC908JL16 Data Sheet, Rev. 1.1
ADCK
ADCK
ADCK
ADCK
)
)
)
)
ACLKEN
X
X
X
X
0
1
0
1
0
1
0
1
38 ADCK + 3 bus clock + 5 µs
21 ADCK + 3 bus clock + 5 µs
41 ADCK + 3 bus clock + 5 µs
18 ADCK + 3 bus clock + 5 µs
Maximum Conversion Time
18 ADCK + 3 bus clock
38 ADCK + 3 bus clock
21 ADCK + 3 bus clock
41 ADCK + 3 bus clock
16 ADCK
36 ADCK
19 ADCK
39 ADCK
Freescale Semiconductor
Table
9-1.

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