C8051F502-IM Silicon Laboratories Inc, C8051F502-IM Datasheet - Page 239
![IC 8051 MCU 64K FLASH 32-QFN](/photos/12/17/121713/c8051f502-im_sml.jpg)
C8051F502-IM
Manufacturer Part Number
C8051F502-IM
Description
IC 8051 MCU 64K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F502-IM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1559 - KIT REF DESIGN CAN DIAGNOSTIC336-1532 - ADAPTER PROG TOOLSTICK F502336-1531 - PLATFORM PROG TOOLSTCK F502336-1528 - DAUGHTER CARD TOOLSTICK F500336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1515-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F502-IM
Manufacturer:
SiliconL
Quantity:
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Part Number:
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Manufacturer:
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23.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated
and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore
the received slave address with a NACK.
If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected.
If the received slave address is acknowledged, zero or more data bytes are received. Software must write
the ACK bit at that time to ACK or NACK the received byte.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 23.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur before the ACK in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 23.7. Typical Slave Write Sequence
W
A
Data Byte
Rev. 1.2
Interrupts
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
C8051F50x/F51x
A
P
239
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