C8051F502-IM Silicon Laboratories Inc, C8051F502-IM Datasheet - Page 6
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C8051F502-IM
Manufacturer Part Number
C8051F502-IM
Description
IC 8051 MCU 64K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F502-IM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1559 - KIT REF DESIGN CAN DIAGNOSTIC336-1532 - ADAPTER PROG TOOLSTICK F502336-1531 - PLATFORM PROG TOOLSTCK F502336-1528 - DAUGHTER CARD TOOLSTICK F500336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1515-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F502-IM
Manufacturer:
SiliconL
Quantity:
146
Company:
Part Number:
C8051F502-IM
Manufacturer:
SILICON
Quantity:
2 000
C8051F50x/F51x
22. Controller Area Network (CAN0) ........................................................................ 218
23. SMBus................................................................................................................... 226
24. UART0 ................................................................................................................... 243
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 252
6
21.5. Sleep Mode and Wake-Up ............................................................................ 207
21.6. Error Detection and Handling ........................................................................ 207
21.7. LIN Registers................................................................................................. 208
22.1. Bosch CAN Controller Operation................................................................... 219
22.2. CAN Registers............................................................................................... 222
23.1. Supporting Documents .................................................................................. 227
23.2. SMBus Configuration..................................................................................... 227
23.3. SMBus Operation .......................................................................................... 227
23.4. Using the SMBus........................................................................................... 229
23.5. SMBus Transfer Modes................................................................................. 236
23.6. SMBus Status Decoding................................................................................ 240
24.1. Baud Rate Generator .................................................................................... 243
24.2. Data Format................................................................................................... 245
24.3. Configuration and Operation ......................................................................... 246
25.1. Signal Descriptions........................................................................................ 253
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 208
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 210
22.1.1. CAN Controller Timing .......................................................................... 219
22.1.2. CAN Register Access............................................................................ 220
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 220
22.2.1. CAN Controller Protocol Registers........................................................ 222
22.2.2. Message Object Interface Registers ..................................................... 222
22.2.3. Message Handler Registers.................................................................. 222
22.2.4. CAN Register Assignment .................................................................... 223
23.3.1. Transmitter vs. Receiver ....................................................................... 228
23.3.2. Arbitration.............................................................................................. 228
23.3.3. Clock Low Extension............................................................................. 228
23.3.4. SCL Low Timeout.................................................................................. 228
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 229
23.4.1. SMBus Configuration Register.............................................................. 229
23.4.2. SMB0CN Control Register .................................................................... 233
23.4.3. Data Register ........................................................................................ 236
23.5.1. Write Sequence (Master) ...................................................................... 237
23.5.2. Read Sequence (Master) ...................................................................... 238
23.5.3. Write Sequence (Slave) ........................................................................ 239
23.5.4. Read Sequence (Slave) ........................................................................ 240
24.3.1. Data Transmission ................................................................................ 246
24.3.2. Data Reception ..................................................................................... 246
24.3.3. Multiprocessor Communications ........................................................... 247
25.1.1. Master Out, Slave In (MOSI)................................................................. 253
25.1.2. Master In, Slave Out (MISO)................................................................. 253
Rev. 1.2