MC9S08AW48CFDE Freescale Semiconductor, MC9S08AW48CFDE Datasheet - Page 105

IC MCU 48K FLASH 48-QFN

MC9S08AW48CFDE

Manufacturer Part Number
MC9S08AW48CFDE
Description
IC MCU 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of MC9S08AW48CFDE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48QFN EP
Family Name
HCS08
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
6.7.14
In addition to the I/O control, port G pins are controlled by the registers listed below.
Freescale Semiconductor
PTGDD[6:0]
PTGPE[6:0]
Reset
Reset
Field
Field
6:0
6:0
W
W
R
R
Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
0
0
0
0
7
7
PTGDD6
PTGPE6
Figure 6-42. Internal Pullup Enable for Port G Bits (PTGPE)
0
0
6
6
Table 6-32. PTGDD Register Field Descriptions
Figure 6-41. Data Direction for Port G (PTGDD)
Table 6-33. PTGPE Register Field Descriptions
PTGDD5
PTGPE5
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
5
PTGDD4
PTGPE4
0
0
4
4
Description
Description
PTGDD3
PTGPE3
3
0
3
0
PTGDD2
PTGPE2
0
0
2
2
Chapter 6 Parallel Input/Output
PTGDD1
PTGPE1
0
0
1
1
PTGDD0
PTGPE0
0
0
0
0
105

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