R5F21102DFP#U0 Renesas Electronics America, R5F21102DFP#U0 Datasheet - Page 104

• Manufacturer Part Number: R5F21102DFP#U0
• Description: IC R8C MCU FLASH 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/10r

Specifications of R5F21102DFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/10 Group
Rev.1.20 Jan 27, 2006
REJ09B0019-0120
Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers
U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 , 1 )
U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( i = 0 , 1 )
b 7
0
b 7
N O T E S :
NOTES:
1 . I f t h e B R G c o u n t s o u r c e i s s w i t c h e d , s e t t h e U i B R G r e g i s t e r a g a i n .
1. Must set the P1_6 bit in the PD1 register to “0” (input).
2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: “000
3. Must set the CKDIR bit to “0” (internal clock) in UART1.
b 6
b6
b 5
b 5
b 4
b 4
b 3
b 3
b 2
b 2
0
b 1
b 1
b 0
page 92 of 180
b 0
U F O R M T r a n s f e r f o r m a t s e l e c t b i t
CKPOL
TXEPT
s y m b o l
C K D I R
s y m b o l
S M D 0
S M D 1
S M D 2
PRYE
S T P S
CLK0
CLK1
P R Y
NCH
(b2)
( b 4 )
(b7)
B i t
B i t
Symbol
Internal/external clock
select bit
Stop bit length select bit
Odd/even parity select bit
Parity enable bit
Reserved bit
S e r i a l i n t e r f a c e m o d e
s e l e c t b i t
Symbol
U0C0
U1C0
BRG count source
select bit
Transmit register empty
flag
Data output select bit
CLK polarity select bit
Reserved bit
U0MR
U1MR
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
B i t n a m e
B i t n a m e
(3)
(2 )
(1)
Address
00AC
00A4
Address
00A0
00A8
0 0 : f
0 1 : f
1 0 : f
1 1 : Avoid this setting
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
0 : TxDi pin is a pin of CMOS output
1 : TxDi pin is a pin of N-channel open-drain output
0 : LSB first
1 : MSB first
0 : 1 s t o p b i t
1 : 2 s t o p b i t s
E f f e c t i v e w h e n P R Y E = 1
0 : O d d p a r i t y
1 : E v e n p a r i t y
0 : P a r i t y d i s a b l e d
1 : P a r i t y e n a b l e d
16
Set to “0”
0 : Transmit data is output at falling edge of transfer clock
1 : Transmit data is output at rising edge of transfer clock
16
b1 b0
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
0 : Internal clock
1 : External clock
Set to “0”
16
16
(transmission completed)
1SIO
8SIO
32SIO
and receive data is input at rising edge
and receive data is input at falling edge
is selected
is selected
is selected
After reset
After reset
08
08
00
00
(1)
16
16
16
16
F u n c t i o n
F u n c t i o n
2
”, “100
2
”, “101
2
”, or “110
13. Serial InterfaceI
2
”.
RW
RW
RW
RW
RW
R W
R W
R W
R W
R W
R W
RW
R W
RW
R W
RO
R W