R5F21102DFP#U0 Renesas Electronics America, R5F21102DFP#U0 Datasheet - Page 65
R5F21102DFP#U0
Manufacturer Part Number
R5F21102DFP#U0
Description
IC R8C MCU FLASH 8K 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/10r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21102FPU0.pdf
(30 pages)
3.R5F21102FPU0.pdf
(201 pages)
Specifications of R5F21102DFP#U0
Core Processor
R8C
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LED, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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R8C/10 Group
Rev.1.20 Jan 27, 2006
REJ09B0019-0120
11. Watchdog Timer
Figure 11.1 Watchdog Timer Block Diagram
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit in the PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it
cannot be set to “0” (watchdog timer interrupt) in a program. Refer to Section 5.3, “Watchdog Timer
Reset” for details.
The divide-by-N value for the prescaler can be chosen to be 16 or 128 with the WDC7 bit in the WDC
register. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,
however, subject to an error due to the prescaler.
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register. After that, the watchdog timer is initialized by
writing to the WDTR register and the counting continues.
In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from
the held value when the modes or state are released.
Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timer-
related registers.
Watchdog timer period =
Internal
reset
signal
Write to WDTR register
CPU clock
page 53 of 180
Prescaler
1/128
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
1/16
WDC7 = 0
WDC7 = 1
CPU clock
Watchdog timer
Set to
“7FFF
16
”
PM12 = 0
PM12 = 1
11. Watchdog Timer
Watchdog timer
interrupt request
Watchdog
timer Reset
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