MCF51CN128CLH Freescale Semiconductor, MCF51CN128CLH Datasheet - Page 30

• Manufacturer Part Number: MCF51CN128CLH
• Description: IC MCU 32BIT 128K FLASH 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51CNr

Specifications of MCF51CN128CLH

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, SCI, SPI
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: MCF51CN
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 24 KB
• Interface Type: I2C, SPI, SCI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 54
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 12 Channel
• Package: 64LQFP
• Device Core: ColdFire
• Family Name: MCF51CN
• Maximum Speed: 50.33 MHz
• Number Of Timers: 2
• For Use With: TWR-MCF51CN - KIT TOWER BOARDTWR-MCF51CN-KIT - KIT TOWER BOARD/SERIAL/ELEVATOR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
30
(CPOL = 1)
(CPOL = 0)
(OUTPUT)
(OUTPUT)
NOTES:
(CPOL = 0)
(CPOL = 1)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
SPSCK
SPSCK
(INPUT)
MISO
MOSI
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SPSCK
SPSCK
NOTES:
SS
MISO
MOSI
SS
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1
(1)
PORT DATA
9
2
5
9
MSB IN
2
MSB OUT
MASTER MSB OUT
4
5
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
MSB IN
6
2
4
1
2
Figure 23. SPI Master Timing (CPHA = 0)
Figure 24. SPI Master Timing (CPHA =1)
1
(2)
6
4
4
BIT 6 . . . 1
BIT 6 . . . 1
(2)
9
12
11
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
LSB OUT
12
11
MASTER LSB OUT
12
11
LSB IN
10
3
3
Freescale Semiconductor
PORT DATA