MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 166

• Manufacturer Part Number: MCHC908MR8VFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Pulse-Width Modulator for Motor Control
Technical Data
166
NOTE:
The filtered fault pin’s logic state is reflected in the respective FPINx bit.
Any write to this bit is overwritten by the pin state. The FFLAGx event bit
is set with each rising edge of the respective fault pin after filtering has
been applied. To clear the FFLAGx bit, the user must write a 1 to the
corresponding FTACKx bit.
If the FINTx bit is set, a fault condition resulting in setting the
corresponding FFLAG bit will also latch a CPU interrupt request. The
interrupt request latch is not cleared until one of these actions occurs:
If prior to a vector fetch the interrupt request latch is cleared by one of
the above actions, a CPU interrupt will no longer be requested. A vector
fetch does not alter the state of the PWMs, the FFLAGx event flag, or
FINTx.
If the FFLAGx or FINTx bits are not cleared during the interrupt service
routine, the interrupt request latch will not be cleared.
FILTERED FAULT PIN
Pulse-Width Modulator for Motor Control (PWMMC)
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•
•
The FFLAGx bit is cleared by writing a 1 to the corresponding
FTACKx bit.
The FINTx bit is cleared. (This will not clear the FFLAGx bit.)
Reset — A reset automatically clears all four interrupt latches.
PWM(s) ENABLED
Figure 9-24. PWM Disabling in Automatic Mode
PWM(S) DISABLED (INACTIVE)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
PWM(S) ENABLED