MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 102

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.8
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected
peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,
if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be
available. This register is used to enable high-speed clocking for those peripherals that support it.
Note:
6.3.8.1
This bit selects the clock speed for the Quad Timer B module.
6.3.8.2
This bit selects the clock speed for the Quad Timer A module.
6.3.8.3
This bit selects the clock speed for the PWM module.
6.3.8.4
This bit selects the clock speed for the I
6.3.8.5
This bit field is reserved. Each bit must be set to 0.
102
•
•
•
•
•
•
•
•
Base + $B
RESET
Read
Write
0 = Quad Timer B clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = Quad Timer B clock rate equals 3X system clock rate, to a maximum 96MHz
0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz
0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz
0 = I
1 = I
Peripheral Clock Rate Register (SIM_PCR)
Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be
disabled before a peripheral clock is reconfigured.
2
2
Quad Timer B Clock Rate (TMRB_CR)—Bit 15
Quad Timer A Clock Rate (TMRA_CR)—Bit 14
Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13
Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12
C module run clock rate equals the system clock rate, to a maximum 32MHz (default)
C module run clock rate equals 3X system clock rate, to a maximum 96MHz
Reserved—Bits 11–0
TMRB_
CR
15
0
Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)
TMRA_
CR
14
0
PWM_
CR
13
0
I2C_
CR
12
0
56F8037/56F8027 Data Sheet, Rev. 7
2
11
C run clock.
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
4
0
0
Freescale Semiconductor
3
0
0
2
0
0
1
0
0
0
0
0