MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 69

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.1
Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base
Address (VBA) and the vector number to determine the vector address, generating an offset into the vector
table for each interrupt.
5.3.2
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0
and I1 bits in its status register.
The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E
core.
5.3.3
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
Fast Interrupts before the core does.
A Fast Interrupt is defined (to the ITCN) by:
Freescale Semiconductor
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
Normal Interrupt Handling
Interrupt Nesting
Fast Interrupt Handling
SR[9] (I1) SR[8] (I0)
IPIC_VALUE[1:0]
0
0
1
1
00
01
10
11
Table 5-1 Interrupt Mask Bit Definition
Table 5-2 Interrupt Priority Encoding
0
1
0
1
56F8037/56F8027 Data Sheet, Rev. 7
No interrupt or SWILP
Current Interrupt
Exceptions Permitted
Priority Level
Priority 2 or 3
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priority 0
Priority 1
Priorities 2, 3
Priority 3
Exception Priority
Priorities 0, 1, 2, 3
Required Nested
Priorities 1, 2, 3
Exceptions Masked
Priorities 2, 3
Priorities 0, 1, 2
Priority 3
Priorities 0, 1
Priority 0
None
Functional Description
69