C8051F045-GQ Silicon Laboratories Inc, C8051F045-GQ Datasheet - Page 150
![IC 8051 MCU 64K FLASH 64TQFP](/photos/12/18/121883/c8051f045-gq_sml.jpg)
C8051F045-GQ
Manufacturer Part Number
C8051F045-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1210
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Price
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Manufacturer:
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C8051F045-GQ
Manufacturer:
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C8051F040/1/2/3/4/5/6/7
12.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic 1. Future product versions may use these bits to implement new features, in
which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-
sponding system function.
150
Bits7-0:
Bits7-0:
Bits7-0:
R/W
R/W
R/W
Bit7
Bit7
Bit7
SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 12.7. DPH: Data Pointer High Byte
SFR Definition 12.6. DPL: Data Pointer Low Byte
SFR Definition 12.5. SP: Stack Pointer
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.5
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
SFR Address:
SFR Address:
SFR Address:
SFR Page:
SFR Page:
SFR Page:
R/W
R/W
Bit0
R/W
Bit0
Bit0
0x81
All Pages
0x83
All Pages
0x82
All Pages
00000000
Reset Value
00000111
00000000
Reset Value
Reset Value
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