C8051F045-GQ Silicon Laboratories Inc, C8051F045-GQ Datasheet - Page 164
C8051F045-GQ
Manufacturer Part Number
C8051F045-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1210
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C8051F040/1/2/3/4/5/6/7
12.17.2.Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes. In Stop mode, the CPU and internal oscillators are stopped, effectively
shutting down all digital peripherals. Each analog peripheral must be shut down individually prior to enter-
ing Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51
performs the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD
timeout of 100 µs.
164
Bits7-3:
Bit1:
Bit0:
R/W
Bit7
—
Reserved.
STOP: STOP Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’.
0: No effect.
1: CIP-51 forced into power-down mode. (Turns off internal oscillator).
IDLE: IDLE Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’.
0: No effect.
1: CIP-51 forced into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and
all peripherals remain active.)
R/W
Bit6
—
SFR Definition 12.18. PCON: Power Control
R/W
Bit5
—
R/W
Bit4
—
Rev. 1.5
R/W
Bit3
—
R/W
Bit2
—
STOP
R/W
Bit1
SFR Address:
SFR Page:
IDLE
R/W
Bit0
0x87
All Pages
00000000
Reset Value
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