MC908AP32CFAE Freescale Semiconductor, MC908AP32CFAE Datasheet - Page 117

• Manufacturer Part Number: MC908AP32CFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3.1 Entering Monitor Mode
Table 8-1
may be entered after a POR and will allow communication at 9600 baud provided one of the following
sets of conditions is met:
If V
frequency is a divide-by-two of the input clock. If PTB0 is high with V
mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTB0 pin low when
entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V
to IRQ1. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
If entering monitor mode without high voltage on IRQ1 (above condition set 2), then all port A pin
requirements and conditions, including the PTB0 frequency divisor selection, are not in effect. This is to
reduce circuit requirements when performing in-circuit programming.
The COP module is disabled in monitor mode based on these conditions:
The second condition states that as long as V
mode, or if V
to IRQ1), then the COP will be disabled. In the latter situation, after V
can be removed from the IRQ1 pin in the interest of freeing the IRQ1 for normal functionality in monitor
mode.
Figure 8-2
V
9600, as the internal bus frequency is automatically set to the external frequency divided by four.
Enter monitor mode with pin configuration shown in
rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See
security bytes, the MCU sends a break signal (10 consecutive logic 0’s) to the host, indicating that it is
ready to receive a command.
Freescale Semiconductor
DD
1. If $FFFE and $FFFF do not contain $FF (programmed state):
2. If $FFFE and $FFFF both contain $FF (erased state):
•
•
TST
voltage is applied to the IRQ1 pin. An external oscillator of 9.8304 MHz is required for a baud rate of
–
–
–
–
If monitor mode was entered as a result of the reset vector being blank (above condition set 2), the
COP is always disabled regardless of the state of IRQ1 or RST.
If monitor mode was entered with V
as V
is applied to IRQ1 and PTB0 is low upon monitor mode entry (above condition set 1), the bus
shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
The external clock is 4.9152 MHz with PTB0 low or 9.8304 MHz with PTB0 high
IRQ1 = V
The external clock is 9.8304 MHz
IRQ1 = V
shows a simplified diagram of the monitor mode entry when the reset vector is blank and just
TST
TST
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial POR reset. Once the part has been
programmed, the traditional method of applying a voltage, V
must be used to enter monitor mode.
is applied to either IRQ1 or RST.
is applied to RST after the initial reset to get into monitor mode (when V
TST
DD
(this can be implemented through the internal IRQ1 pullup)
MC68HC908AP A-Family Data Sheet, Rev. 3
TST
on IRQ1 (condition set 1), then the COP is disabled as long
TST
NOTE
is maintained on the IRQ1 pin after entering monitor
Figure 8-1
by pulling RST low and then high. The
TST
TST
applied to IRQ1 upon monitor
is applied to the RST pin, V
TST
, to IRQ1
8.4
Functional Description
Security.) After the
TST
TST
was applied
is applied
TST
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