C8051F060-GQ Silicon Laboratories Inc, C8051F060-GQ Datasheet - Page 106

• Manufacturer Part Number: C8051F060-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F060-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1213

C8051F060/1/2/3/4/5/6/7
106
Bit7:
Bits6-5:
Bits4-3:
Bits2-0:
MSB
DAC0EN
R/W
Bit7
MSB
DAC0EN: DAC0 Enable Bit.
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode.
1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational.
UNUSED. Read = 00b; Write = don’t care.
DAC0MD1-0: DAC0 Mode Bits.
00: DAC output updates occur on a write to DAC0H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
DAC0DF2-0: DAC0 Data Format Bits:
000:
001:
010:
011:
1xx:
MSB
R/W
Bit6
-
The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least
significant byte is in DAC0L.
The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least
significant 7-bits are in DAC0L[7:1].
The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least
significant 6-bits are in DAC0L[7:2].
The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least
significant 5-bits are in DAC0L[7:3].
The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least
significant 4-bits are in DAC0L[7:4].
MSB
DAC0H
DAC0H
DAC0H
DAC0H
DAC0H
R/W
Bit5
MSB
Figure 8.4. DAC0CN: DAC0 Control Register
-
DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1
R/W
Bit4
Rev. 1.2
R/W
Bit3
R/W
Bit2
LSB
R/W
Bit1
DAC0L
DAC0L
DAC0L
DAC0L
DAC0L
LSB
SFR Address:
DAC0DF0
SFR Page:
R/W
Bit0
LSB
LSB
0xD4
0
Reset Value
00000000
LSB