MC56F8346VFVE Freescale Semiconductor, MC56F8346VFVE Datasheet
MC56F8346VFVE
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MC56F8346VFVE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8346 Rev. 15 01/2007 freescale.com ...
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... Corrected typo in Table 10-12. Corrected temperature Table 10-24 and new graphs in Table 10-1. and clarified Section 12.3. Table 10-1; also removed overall Table 13-1. 10-1). Deleted formula for Max Ambient Table 10-14 by increasing Freescale Semiconductor Preliminary ...
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... Added the following note to the description of the TRST signal in Note: For normal operation, connect TRST directly to V debugging environment, TRST may be tied to V Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Preliminary Description of Change through a 2.2K resistor through a 1K resistor ...
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... Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... Timer D or GPIOE 2 FlexCAN SPI0 or GPIOE 4 56F8346/56F8146 Block Diagram - 144 LQFP Freescale Semiconductor Preliminary • Temperature Sensor • two Quadrature Decoders • Optional On-Chip Regulator • FlexCAN module • Two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • four general-purpose Quad Timers • ...
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... Thermal Design Considerations . . . . . . . 174 12.2 Electrical Design Considerations . . . . . . 175 12.3 Power Distribution and I/O Ring Part 13 Ordering Information . . . . . . . . . . 177 56F8346 Technical Data, Rev. 15 Interrupt Timing . . . . . . . . . . . . . . . 150 Timing 152 Timing 158 Parameters . . . . . . . . . . . . . . . . . . . 161 Information . . . . . . . . . . . . . . . . . . . 167 Information . . . . . . . . . . . . . . . . . . . 169 Implementation . . . . . . . . . . . . . . . . 176 Freescale Semiconductor Preliminary ...
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... Table 1-1 outlines the key differences between the 56F8346 and 56F8146 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8346 60MHz/60 MIPS 4KB 8KB — ...
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... Timer D with two pins — In the 56F8146, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO • Optional On-Chip Regulator • FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive 8 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... The 56F8346 and 56F8146 support program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Device Description ...
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... Program Flash memory area, which can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased. 10 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Descriptions, to see which signals are multiplexed with those of other peripherals. Freescale Semiconductor Preliminary Figure 1-1 and Figure 56F8346 Technical Data, Rev ...
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... C input channel as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 12 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... I/O to the FIU over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. Freescale Semiconductor Preliminary pdb_m[15:0] pab[20:0] cdbw[13:0] ...
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... SIM COP Reset COP 2 FlexCAN 12 PWMA SYNC Output 13 PWMB SYNC Output ch3i ch2i 1 Timer C ch3i ch2i 8 ADCB 8 ADCA 1 TEMP_SENSE Note: ADCA and ADCB use the same volt- age reference circuit with REFH and V pins. REFMID REFN REFLO Freescale Semiconductor REFP, Preliminary ...
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... DSP56800E Reference Manual 56F8300 Peripheral User Manual 56F8300 SCI/CAN Bootloader User Manual 56F8346/56F8146 Technical Data Sheet Errata Freescale Semiconductor Preliminary Table 1-2 Bus Signal Names Function Program Memory Interface Primary Data Memory Interface Bus 1 , words, and long data types. Data is written ...
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... A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol PIN PIN PIN PIN 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 16 Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted 56F8346 Technical Data, Rev Voltage Freescale Semiconductor Preliminary ...
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... Temperature Sense Dedicated GPIO 1. If the on-chip regulator is disabled, the V 2. Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO Freescale Semiconductor Preliminary Figure 2-1. In Table 2-2, each table row describes the signal or signals pins serve as 2 ...
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... Quadrature Decoder 0 or Quad Timer A or GPIO SPI0 or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA or GPIO PWMB or GPIO ADCA REF ADCB Temperature Sensor FlexCAN QUAD TIMER C and D or GPIO Imterrupt/ Program Control 1 (144-pin LQFP) Freescale Semiconductor Preliminary ...
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... RXD0 (GPIOE1) TXD1 (GPIOD6) SCI 1 RXD1 (GPIOD7) or GPIO JTAG/ EOnCE Port Figure 2-2 56F8146 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary V DD_IO 7 PHASEA0 (TA0, GPIOC4 PHASEB0 (TA1, GPIOC5) 1 INDEX0 (TA2, GPIOC6) ...
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... OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. V — These pins provide ground for chip logic and I/O drivers. SS ADC Analog Ground — This pin supplies an analog ground to the ADC modules. 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... CLKMODE 87 Input EXTAL 82 Input XTAL 81 Input/ Output Freescale Semiconductor Preliminary State During Reset Input On-Chip Regulator Disable — Tie this pin enable the on-chip regulator SS Tie this pin disable the on-chip regulator DD This pin is intended static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation ...
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... Port A GPIO — These six GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA8, clear bit 8 in the GPIOA_PUR register. 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... A12 23 (GPIOA4) A13 24 (GPIOA5) A14 25 (GPIOA6) A15 26 (GPIOA7) Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Address Bus — specify two of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control ...
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... At reset, these pins default to the EMI Data Bus function. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF9, clear bit 9 in the GPIOF_PUR register. 56F8346 Technical Data, Rev. 15 for further information on when this Freescale Semiconductor Preliminary ...
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... D14 136 (GPIOF7) D15 137 Input/ Output (GPIOF8) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Data Bus — D14 specify part of the data for external program output is or data memory accesses. disabled, pull-up is Most designs will want to change the DRV state to DRV = 1 instead of enabled using the default setting ...
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... PS is tri-stated when the external bus is inactive. CS0 resets to provide the PS function as defined on the 56F80x devices. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOD_PUR register. 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... Output GPIOD1 49 (CS3) TXD0 4 Output (GPIOE0) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Data Memory Select — This signal is actually CS1 in the EMI, output is which is programmed at reset for compatibility with the 56F80x DS disabled, signal asserted low for external data memory access. ...
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... JTAG/EOnCE port sampled on the rising edge internally of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. 56F8346 Technical Data, Rev. 15 Signal Description through a 2.2K resistor. DD Freescale Semiconductor Preliminary ...
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... Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Reset In reset, Test Data Output — This tri-stateable output pin provides a serial output is output data stream from the JTAG/EOnCE port driven in the disabled, shift-IR and shift-DR controller states, and changes on the falling pull-up is edge of TCK ...
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... TA3 — Timer A, Channel 3 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is HOME0. To deactivate the internal pull-up resistor, clear bit 7 of the GPIOC_PUR register. 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... Input/ Output MISO0 131 Input/ Output (GPIOE6) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, SPI 0 Serial Clock — In the master mode, this pin serves as an pull-up output, clocking slaved listeners. In slave mode, this pin serves as enabled the data clock input. Port E GPIO — ...
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... In the 56F8346, the default state after reset is PHASEA1. In the 56F8146, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOC_PUR register. 56F8346 Technical Data, Rev. 15 Part Freescale Semiconductor Preliminary ...
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... Schmitt Input/ Output (MOSI1) Schmitt Input/ Output (GPIOC1) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1. pull-up enabled TB1 — Timer B, Channel 1 SPI 1 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device ...
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... In the 56F8346, the default state after reset is HOME1. In the 56F8146, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register. 56F8346 Technical Data, Rev. 15 Part 6.5.8. Part 6.5.8. Freescale Semiconductor Preliminary ...
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... FAULTA2 74 PWMB0 34 Output PWMB1 35 PWMB2 36 PWMB3 39 PWMB4 40 PWMB5 41 Freescale Semiconductor Preliminary State During Signal Description Reset In reset, PWMA0 - 5 — These are six PWMA outputs. output is disabled, pull-up is enabled Input, ISA0 - 2 — These three input current status pins are used for pull-up ...
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... Output 0.1μF low ESR capacitor. Analog V — Analog Reference Voltage Low. This should normally REFLO Input be connected to a low-noise V 56F8346 Technical Data, Rev. 15 Part 6.5.8. Part 6.5.8. must be less REFH — Internal pins for voltage reference . SSA Freescale Semiconductor Preliminary ...
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... Open Drain Output TC0 118 Schmitt Input/ Output (GPIOE8) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Analog ANB0 - 3 — Analog inputs to ADC B, channel 0 Input Analog ANB4 - 7 — Analog inputs to ADC B, channel 1 Input Analog Temperature Sensor Diode — This signal connects to an on-chip ...
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... To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Output Reset Output — This output reflects the internal reset state of the chip. 56F8346 Technical Data, Rev. 15 Part 6.5.6 for details. Part 6.5.6 for details. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... Signal Name Pin No. Type EXTBOOT 112 Schmitt Input EMI_MODE 143 Schmitt Input Freescale Semiconductor Preliminary State During Signal Description Reset Input, External Boot — This input is tied to V pull-up boot from off-chip memory (assuming that the on-chip Flash enabled memory is not in a secure state). Otherwise tied to ground. For ...
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... Detector Figure 3-1 OCCS Block Diagram Table 10-15. A recommended crystal oscillator circuit is shown 56F8346 Technical Data, Rev. 15 Figure 3-1 shows the ZSRC SYS_CLK2 Source to SIM PLLCOD Postscaler Postscaler CLK ÷ 1,2,4,8 Bus Interface LCK Loss of Reference Clock Interrupt Freescale Semiconductor Preliminary ...
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... A typical ceramic resonator circuit is shown in Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. Freescale Semiconductor Preliminary EXTAL XTAL ...
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... Note: When using an external clocking source XTAL EXTAL with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL V External register should be set Clock 56F8346 Technical Data, Rev. 15 CLKMODE = 0 Figure 3-4. The external clock Freescale Semiconductor Preliminary ...
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... Table 4-1 Chip Memory Configurations On-Chip Memory 56F8346 Program Flash 128KB Data Flash 8KB Program RAM 4KB Freescale Semiconductor Preliminary Table 4-1. Flash memories’ restrictions are Table 4-1. 56F8146 Use Restrictions 128KB Erase / Program via Flash interface unit and word writes to CDBW — ...
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... Mode 0 – Internal Boot; EMI is configured to use 16 address lines Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin Chip Operating Mode 56F8346 Technical Data, Rev. 15 Use Restrictions 4-2. Table 4-4 shows the memory Freescale Semiconductor Preliminary ...
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... The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over Freescale Semiconductor Preliminary 2 EMI_MODE = 0 ...
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... OnCE Trace Buffer P:$14 OnCE Transmit Register Empty P:$16 OnCE Receive Register Full Reserved P:$1C SW Interrupt 2 P:$1E SW Interrupt 1 P:$20 SW Interrupt 0 P:$22 IRQA P:$24 IRQB Reserved P:$28 Low Voltage Detector (power sense) P:$2A PLL 56F8346 Technical Data, Rev. 15 Part Freescale Semiconductor Preliminary ...
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... SCI1 45 0-2 SCI1 46 0-2 DEC1 47 0-2 DEC1 48 0-2 DEC0 49 0-2 Freescale Semiconductor Preliminary Vector Base Interrupt Function Address + P:$2C FM Access Error Interrupt P:$2E FM Command Complete P:$30 FM Command, data and address Buffers Empty Reserved P:$34 FLEXCAN Bus Off P:$36 FLEXCAN Error ...
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... ADC B Conversion Compete / End of Scan P:$94 ADC A Conversion Complete / End of Scan P:$96 ADC B Zero Crossing or Limit Error P:$98 ADC A Zero Crossing or Limit Error P:$9A Reload PWM B P:$9C Reload PWM A P:$9E PWM B Fault P:$A0 PWM A Fault P:$A2 SW Interrupt LP 56F8346 Technical Data, Rev (Continued) Freescale Semiconductor Preliminary ...
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... The Data RAM is organized 32-bit memory to allow single-cycle long-word operations. 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Freescale Semiconductor Preliminary Table 4-6 Data Memory Map ...
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... Technical Data, Rev. 15 Data Memory FM_BASE + $14 Banked Registers Unbanked Registers FM_BASE + $00 8KB Note: Data Flash is NOT available in the 56F8146 device. Sector Size Page Size bits 512 x 16 bits 256 x 16 bits 256 x 16 bits bits 256 x 16 bits Freescale Semiconductor Preliminary ...
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... OCR (bits) X:$FF FFFC OCLSR (8 bits) X:$FF FFFD OTXRXSR (8 bits) X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 Freescale Semiconductor Preliminary Table 4-8 EOnCE Memory Map Reserved External Signal Control Register Reserved Breakpoint Unit [0] Counter Reserved Breakpoint 1 Unit [0] Mask Register ...
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... GPIOB X:$00 F300 GPIOC X:$00 F310 GPIOD X:$00 F320 56F8346 Technical Data, Rev. 15 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 Freescale Semiconductor Preliminary ...
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... Address Offset CSBAR 0 $0 CSBAR 1 $1 CSBAR 2 $2 CSBAR 3 $3 CSBAR 4 $4 CSBAR 5 $5 CSBAR 6 $6 CSBAR 7 $7 Freescale Semiconductor Preliminary Prefix Base Address GPIOE X:$00 F330 GPIOF X:$00 F340 SIM X:$00 F350 LVI X:$00 F360 FM X:$00 F400 FC X:$00 F800 (EMI_BASE = $00 F020) ...
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... Freescale Semiconductor Preliminary ...
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... TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description $5 Counter Register $6 Control Register $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register ...
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... Counter Register $6 Control Register $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserved $10 Compare Register 1 $11 Compare Register 2 $12 Capture Register $13 Load Register $14 Hold Register 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset Register Description $15 Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A ...
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... Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register $23 Load Register $24 Hold Register $25 Counter Register $26 Control Register 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... Quad Timer D is NOT available in the 56F8146 device Register Acronym TMRD0_CMP1 TMRD0_CMP2 TMRD0_CAP TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR Freescale Semiconductor Preliminary (TMRC_BASE = $00 F0C0) Address Offset $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved ...
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... Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register 56F8346 Technical Data, Rev. 15 Register Description Freescale Semiconductor Preliminary ...
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... PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register (PWMA_BASE = $00 F140) ...
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... Channel Control Register $11 Port Register $12 PWM Internal Correction Control Register (DEC0_BASE = $00 F180) Address Offset Register Description $0 Decoder Control Register $1 Filter Interval Register $2 Watchdog Time-out Register $3 Position Difference Counter Register $4 Position Difference Counter Hold Register 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... DEC1_DECCR DEC1_FIR DEC1_WTR DEC1_POSD DEC1_POSDH DEC1_REV DEC1_REVH DEC1_UPOS DEC1_LPOS DEC1_UPOSH DEC1_LPOSH DEC1_UIR DEC1_LIR DEC1_IMR Freescale Semiconductor Preliminary (DEC0_BASE = $00 F180) Address Offset Register Description $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register $9 Upper Position Hold Register ...
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... IRQ Pending Register 0 $12 IRQ Pending Register 1 $13 IRQ Pending Register 2 $14 IRQ Pending Register 3 $15 IRQ Pending Register 4 $16 IRQ Pending Register 5 $17 Reserved $1D Interrupt Control Register (ADCA_BASE = $00 F200) Address Offset Register Description $0 Control Register 1 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $1 Control Register 2 $2 Zero Crossing Control Register $3 Channel List Register 1 $4 Channel List Register 2 $5 Sample Disable Register ...
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... Result Register 0 $A Result Register 1 $B Result Register 2 $C Result Register 3 $D Result Register 4 $E Result Register 5 $F Result Register 6 $10 Result Register 7 $11 Low Limit Register 0 $12 Low Limit Register 1 $13 Low Limit Register 2 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ADCB_POWER ADCB_CAL Table 4-22 Temperature Sensor Register Address Map Temperature Sensor is NOT available in the 56F8146 device Register Acronym TSENSOR_CNTL Freescale Semiconductor Preliminary (ADCB_BASE = $00 F240) Address Offset Register Description $14 Low Limit Register 3 $15 Low Limit Register 4 $16 Low Limit Register 5 ...
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... F2A0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register $3 Data Transmitter Register (SPI1_BASE = $00 F2B0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... OSCTL Table 4-29 GPIOA Registers Address Map Address Offset Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR Freescale Semiconductor Preliminary (SPI1_BASE = $00 F2B0) Address Offset Register Description $3 Data Transmitter Register (COP_BASE = $00 F2C0) Address Offset Register Description $0 Control Register $1 Time Out Register ...
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... See Table 4-4 for details 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 00FF — Reset Value 0 x 07FF 0 x 0000 0 x 0000 0 x 07FF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 Freescale Semiconductor Preliminary ...
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... GPIOD_RAWDATA Table 4-33 GPIOE Registers Address Map Register Acronym Address Offset GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR Freescale Semiconductor Preliminary (GPIOC_BASE = $00 F310) Register Description $8 Interrupt Edge-Sensitive Register $9 Push-Pull Mode Register $A Raw Data Input Register (GPIOD_BASE = $00 F320) Register Description $0 ...
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... Pull-up Disable Register Reserved 56F8346 Technical Data, Rev. 15 Reset Value 0 x 3FFF — Reset Value 0 x FFFF 0 x 0000 0 x 0000 0 x FFFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x FFFF — Register Description Freescale Semiconductor Preliminary ...
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... Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 Freescale Semiconductor Preliminary (SIM_BASE = $00 F350) Address Offset Register Description $A Clock Out Select Register $B Quad Decoder 1 / Timer B / SPI 1 Select Register $C Peripheral Clock Enable Register ...
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... Receive Buffer 15 Mask Low Register Reserved $10 Error and Status Register $11 Interrupt Masks 1 Register $12 Interrupt Flags 1 Register $13 Receive and Transmit Error Counters Register Reserved Reserved Reserved $40 Message Buffer 0 Control / Status Register $41 Message Buffer 0 ID High Register 56F8346 Technical Data, Rev. 15 Register Description Freescale Semiconductor Preliminary ...
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... FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $42 Message Buffer 0 ID Low Register $43 Message Buffer 0 Data Register $44 Message Buffer 0 Data Register $45 Message Buffer 0 Data Register $46 Message Buffer 0 Data Register ...
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... Message Buffer 6 Data Register Reserved $78 Message Buffer 7 Control / Status Register $79 Message Buffer 7 ID High Register $7A Message Buffer 7 ID Low Register $7B Message Buffer 7 Data Register $7C Message Buffer 7 Data Register $7D Message Buffer 7 Data Register $7E Message Buffer 7 Data Register Reserved 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $80 Message Buffer 8 Control / Status Register $81 Message Buffer 8 ID High Register $82 Message Buffer 8 ID Low Register $83 Message Buffer 8 Data Register ...
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... Message Buffer 14 ID Low Register $B3 Message Buffer 14 Data Register $B4 Message Buffer 14 Data Register $B5 Message Buffer 14 Data Register $B6 Message Buffer 14 Data Register Reserved $B8 Message Buffer 15 Control / Status Register $B9 Message Buffer 15 ID High Register $BA Message Buffer 15 ID Low Register 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... Two programmable Fast Interrupts • Notification to SIM module to restart clocks out of Wait and Stop modes • Drives initial address on the address bus after reset For further information, see Table Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $BB Message Buffer 15 Data Register ...
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... Permitted Exceptions SR[8] 0 Priorities Priorities Priorities Priority 3 Current Interrupt 1 Priority Level No Interrupt or SWILP Priority 0 Priority 1 Priorities Part 5.6.30.2. 56F8346 Technical Data, Rev. 15 Masked Exceptions None Priority 0 Priorities 0, 1 Priorities Required Nested Exception Priority Priorities Priorities Priorities 2, 3 Priority 3 Freescale Semiconductor Preliminary ...
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... Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this mode by default. Freescale Semiconductor Preliminary any0 Level 0 82 -> Priority Encoder any3 Level 3 82 -> ...
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... Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 56F8346 Technical Data, Rev. 15 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 Freescale Semiconductor Preliminary ...
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... FIVAH0 FIM1 FIVAL1 $10 FIVAH1 Figure 5-2 ITCN Register Map Summary Freescale Semiconductor Preliminary Table 5-3 ITCN Register Summary Register Name IRQ Pending Register 2 IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Interrupt Control Register STPCNT IPL FMERR IPL LOCK IPL ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through PENDING [16:2] PENDING [32:17] PENDING [48:33] PENDING [64:49] PENDING [80:65 VAB STPCNT IPL 56F8346 Technical Data, Rev PEND IRQB IRQA 1 IRQB STATE STATE INT_DIS EDG Freescale Semiconductor Preliminary 0 1 ING [81] IRQA EDG ...
Page 85
... IRQ is priority level 3 5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 Freescale Semiconductor Preliminary ...
Page 86
... IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default FMERR IPL LOCK IPL LVI IPL 56F8346 Technical Data, Rev IRQB IPL IRQA IPL Freescale Semiconductor Preliminary 0 0 ...
Page 87
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.3.7 External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 87 ...
Page 88
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level FCMSGBUF IPL FCWKUP IPL 56F8346 Technical Data, Rev FCERR IPL FCBOFF IPL Freescale Semiconductor Preliminary ...
Page 89
... FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 89 ...
Page 90
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SPI1_RCV IPL IPL 56F8346 Technical Data, Rev GPIOA IPL GPIOB IPL GPIOC IPL Freescale Semiconductor Preliminary ...
Page 91
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 91 ...
Page 92
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SCI1_RCV SCI1_RERR IPL IPL IPL 56F8346 Technical Data, Rev SCI1_TIDL SCI1_XMIT SPI0_XMIT IPL IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 93
... IRQ is priority level 2 5.6.6.8 SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 93 ...
Page 94
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level TMRD2 IPL TMRD1 IPL TMRD0 IPL 56F8346 Technical Data, Rev DEC0_XIRQ DEC0_HIRQ IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 95
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 95 ...
Page 96
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level TMRB2 IPL TMRB1 IPL TMRB0 IPL 56F8346 Technical Data, Rev TMRC3 IPL TMRC2 IPL TMRC1 IPL Freescale Semiconductor Preliminary 0 0 ...
Page 97
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 97 ...
Page 98
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SCI0_TIDL SCI0_XMIT IPL IPL 56F8346 Technical Data, Rev TMRA3 IPL TMRA2 IPL TMRA1 IPL IPL Freescale Semiconductor 0 0 Preliminary ...
Page 99
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 99 ...
Page 100
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 100 PWMA_RL PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL IPL 56F8346 Technical Data, Rev ADCA_CC ADCB_CC IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 101
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions 101 ...
Page 102
... Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5. 102 VECTOR BASE ADDRESS Part 5.3.1 for details 56F8346 Technical Data, Rev FAST INTERRUPT Freescale Semiconductor Preliminary ...
Page 103
... Reserved—Bits 15–7 This bit field is reserved or not implemented read as 0, but cannot be modified by writing. 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service Freescale Semiconductor Preliminary ...
Page 104
... FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.18 IRQ Pending 0 Register (IRQP0) Base + $ Read Write RESET Figure 5-20 IRQ Pending 0 Register (IRQP0) 104 FAST INTERRUPT 1 VECTOR ADDRESS LOW PENDING [16: 56F8346 Technical Data, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
Page 105
... IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [32:17] ...
Page 106
... IRQ pending for this vector number • IRQ pending for this vector number 5.6.23 IRQ Pending 5 Register (IRQP5) Base + $ Read Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 106 PENDING [64:49 PENDING [80:65 56F8346 Technical Data, Rev PEND Freescale Semiconductor Preliminary ING [81] 1 ...
Page 107
... Base + $ Read INT IPIC Write RESET Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • interrupt is being sent to the 56800E core Freescale Semiconductor Preliminary VAB INT_DIS 56F8346 Technical Data, Rev. 15 ...
Page 108
... IRQB Edge Pin (IRQB Edg)—Bit 1 This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait modes automatically level-sensitive. • IRQB interrupt is a low-level sensitive (default) • IRQB interrupt is falling-edge sensitive. 108 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
Page 109
... Reset sequencing • Clock generation & distribution • Stop/Wait control • Pull-up enables for selected peripherals • System status registers • Registers for software access to the JTAG ID of the chip Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Resets 109 ...
Page 110
... Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip 110 56F8346 Technical Data, Rev clock cycles. Freescale Semiconductor Preliminary ...
Page 111
... The reset state for MB and MA will depend on the Flash secured state. See information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For all other bits, see the DSP56800E Reference Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. Freescale Semiconductor Preliminary ...
Page 112
... Technical Data, Rev. 15 Section Location 6.5.1 6.5.2 6.5.3 6.5.3 6.5.3 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.7 6.5.8 6.5.9 6.5. EMI_ ONCE SW STOP_ MODE EBL RST DISABLE DISABLE SWR COPR EXTR POR CTRL JTAG 0 A20 CLKDIS CLKOSEL Freescale Semiconductor 0 WAIT_ Preliminary ...
Page 113
... Stop Disable (STOP_DISABLE)—Bits 3–2 • STOP mode will be entered when the 56800E core executes a STOP instruction • The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be reprogrammed in the future Freescale Semiconductor Preliminary ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA ...
Page 114
... Reset or by software. Writing this bit position will set the bit, while writing the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low. 114 56F8346 Technical Data, Rev SWR COPR EXTR POR 0 0 Freescale Semiconductor Preliminary ...
Page 115
... This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $11F4. Base + $ Read Write RESET Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $401D. Freescale Semiconductor Preliminary FIELD ...
Page 116
... This bit controls the pull-up resistors on the IRQA and IRQB pins. 6.5.6.7 XBOOT—Bit 9 This bit controls the pull-up resistors on the EXTBOOT pin. 116 Figure 6-8) corresponds to a functional group of pins. See RESET IRQ XBOOT PWMB PWMA0 56F8346 Technical Data, Rev CTRL JTAG Freescale Semiconductor Preliminary ...
Page 117
... CLKOSR. The default state is for the peripheral function of GPIOB[7: programmed as A[23:20]. This can be changed by altering A[23:20], as shown in Base + $ Read Write RESET Figure 6-9 CLKO Select Register (SIM_CLKOSR) 6.5.7.1 Reserved—Bits 15–10 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary A23 A22 A21 56F8346 Technical Data, Rev ...
Page 118
... Reserved for factory test—SYS_CLK2 (from OCCS) • 01110 = Reserved for factory test—SYS_CLK_DIV2 • 01111 = Reserved for factory test—SYS_CLK_D • 10000 = ADCA clock • 10001 = ADCB clock 118 56F8346 Technical Data, Rev. 15 Figure 3-4) Freescale Semiconductor Preliminary ...
Page 119
... Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIOC[3: programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers. Quad Timer Controlled SPI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Freescale Semiconductor Preliminary GPIOC_PER Register GPIO Controlled 0 1 ...
Page 120
... See the “Switch Matrix for Inputs to the Timer” table in the 56F8300 Peripheral User Manual for the definition of the timer inputs based on the Quad Decoder Mode configuration. See SPI controls for determining the direction of each of the SPI pins Freescale Semiconductor Preliminary ...
Page 121
... Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 Analog-to-Digital Converter A Enable (ADCA)—Bit 13 Each bit controls clocks to the indicated peripheral. • Clocks are enabled Freescale Semiconductor Preliminary ...
Page 122
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 122 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
Page 123
... If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Register Descriptions ...
Page 124
... This field represents the upper two address bits of the “hard coded” I/O short address. Base + $ Read Write RESET Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 124 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction ISAL[21: 56F8346 Technical Data, Rev. 15 Instruction Portion ISAL[23:22 Freescale Semiconductor Preliminary ...
Page 125
... All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Freescale Semiconductor Preliminary Part 3 On-Chip Clock Synthesis Peripheral Clocks ...
Page 126
... Resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock. 126 D Q D-FLOP D-FLOP C R Reset Note: Wait disable circuit is similar 56F8346 Technical Data, Rev. 15 56800E STOP_DIS Part 6.5.1. This procedure 21 clock cycles to permit Freescale Semiconductor Preliminary ...
Page 127
... P-space, and start executing code from the Boot Flash at address 0x02_0000. This security affords protection only to applications in which the device operates in internal Flash security Freescale Semiconductor Preliminary 56F8346 Technical Data, Rev. 15 Operation with Security Enabled ...
Page 128
... FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. 128 Figure 7-1. FM_CLKDIV[6] will map to the 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
Page 129
... TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. Freescale Semiconductor Preliminary Flash Memory ...
Page 130
... There are six GPIO ports defined on the 56F8346/56F8146. The width of each port and the associated peripheral function is shown in shown in Table 8-3. 130 4-29 through Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is 56F8346 Technical Data, Rev. 15 4-34 define the actual reset values of Freescale Semiconductor Preliminary ...
Page 131
... Dedicated GPIO 2 pins - EMI CSn pins - EMI CSn - Not available in this package 2 pins - SCI1 2 pins - EMI CSn 3 pins - PWMB current sense Freescale Semiconductor Preliminary Peripheral Function Peripheral Function 56F8346 Technical Data, Rev. 15 Configuration Reset Function EMI Address EMI Address N/A ...
Page 132
... Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 13 Peripheral 56F8346 Technical Data, Rev. 15 Reset Function SCI0 EMI Address SPI0 TMRC N/A GPIO N/A EMI Data Functional Signal Package Pin A10 21 A11 22 A12 23 A13 24 A14 25 A15 26 A0 138 Freescale Semiconductor Preliminary ...
Page 133
... Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8346/56F8146 Pins in italics are NOT available in the 56F8146 device GPIO Port GPIOB 1 This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset. GPIOC Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 1 GPIO ...
Page 134
... GPIO Port GPIOD 134 Reset GPIO Bit Function 0 GPIO 1 GPIO 2 N/A 3 N/A 4 N/A 5 N/A 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 56F8346 Technical Data, Rev. 15 Functional Signal Package Pin CS2 48 CS3 49 TXD1 42 RXD1 CS0 CS1 47 ISB0 50 ISB1 52 ISB2 53 Freescale Semiconductor Preliminary ...
Page 135
... Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8346/56F8146 Pins in italics are NOT available in the 56F8146 device GPIO Port GPIOE Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral 1 Peripheral 2 Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral ...
Page 136
... Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 13 Peripheral 14 Peripheral 15 Peripheral marketing representative 56F8346 Technical Data, Rev. 15 Functional Signal Package Pin D10 32 D11 133 D12 134 D13 135 D14 136 D15 137 authorized distributor Freescale Semiconductor Preliminary for ...
Page 137
... Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage Input Voltage (digital) Input Voltage (analog) Output Voltage Output Voltage (open drain) Freescale Semiconductor Preliminary are stress ratings only, and functional operation at the maximum CAUTION of any voltages (V ...
Page 138
... Comments Symbol R θJA 56F8346 Technical Data, Rev. 15 Min Max -40 125 -40 105 -40 150 -40 125 -55 150 -55 150 Typ Max Unit — — V — — V — — Value Unit 144-pin LQFP 47.1 °C/W Freescale Semiconductor Unit °C °C °C °C °C °C Notes 2 Preliminary ...
Page 139
... Note: The 56F8146 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8146 device. Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Freescale Semiconductor Preliminary Table 10-3 Thermal Characteristics Comments Symbol R θJMA Four layer board (2s2p) R θJMA ...
Page 140
... DDA DDA 2 — V +0.3 DDA -0.3 — 0.8 — — -4 — — -8 — — -12 — — 4 — — 8 — — 12 -40 — 125 -40 — 105 10,000 — — Cycles 10,000 — — Cycles 15 — — Years Freescale Semiconductor Preliminary °C °C ...
Page 141
... High Impedance State Schmitt Trigger Input V HYS Hysteresis Input Capacitance C INC (EXTAL/XTAL) Output Capacitance C OUTC (EXTAL/XTAL) Input Capacitance C IN Output Capacitance C OUT Freescale Semiconductor Preliminary Table 10-4 Notes Min Typ 2.4 — — — Pin Groups — 0 Pin Group Pin Group 13 — 0 Pin Group 12 — ...
Page 142
... External Clock is off 0μA 145μA • All peripheral clocks are off • ADC powered off • PLL powered off = ( REFH REFLO 56F8346 Technical Data, Rev. 15 Typ Max Units 1.8 1.9 2.14 — 2.7 — 110 130 Test Conditions ) Freescale Semiconductor μA Preliminary ...
Page 143
... Load) Loaded Output Voltage (200mA load) Line Regulation @ 250mA load (V 33 ranges from 3.0V to 3.6V) DD Short Circuit Current (output shorted to ground) Bias Current Power-down Current Short-Circuit Tolerance (output shorted to ground) Freescale Semiconductor Preliminary DD_ADC DD_OSC_PLL DD_IO 13μA 50mA 2.5mA 13μA 65μ ...
Page 144
... ACC R — 0.104 ES 56F8346 Technical Data, Rev. 15 Typical Max Unit 0 0. — 200 ps — 175 ps 1 μA 100 150 Max Unit — mV/°C 28 °C 128 °C 153 °C — V 3.6 V μA 10 μA 250 0 6.7 °C — °C / bit Freescale Semiconductor Preliminary ...
Page 145
... Flash module contains two interleaved memories. 2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes. Freescale Semiconductor Preliminary Table Figure 10-1 ...
Page 146
... Technical Data, Rev Typ Max Unit — 120 MHz — — — 10 — 90% 50% 10 fall rise Min Typ Max 4 8 8.4 160 — 260 — /2), please refer to the OCCS chapter in OUT Freescale Semiconductor Unit MHz MHz ms Preliminary ...
Page 147
... Peripheral User Manual details what each wait state field controls. When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler ÷ 1), clock and prescaler is set to clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE Freescale Semiconductor Preliminary Symbol Min T ...
Page 148
... When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. 148 t ARDD t ARDA WAC t WRRD t DOH t t DOS AD Data Out 56F8346 Technical Data, Rev RDA t t RDRD RD t RDWR t RDD t DRD Data In Freescale Semiconductor Preliminary ...
Page 149
... WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted 1. N/A, since device captures data before it deasserts RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads. Freescale Semiconductor Preliminary Wait States Symbol D Configuration WWS=0 -2 ...
Page 150
... IF t 18T IF - FAST 5 t 1.5T IW 56F8346 Technical Data, Rev. 15 1,2 Typical Unit See Figure Max 21 ns 10-5 — ns 10-5 64T ns 10-5 — ns 10-6 — ns 10-7 — — ns 10-7 — — ns 10-8 — — ns 10-9 — — Freescale Semiconductor Preliminary ...
Page 151
... IRQB General Purpose I/O Pin t IG IRQA , IRQB Figure 10-7 External Level-Sensitive Interrupt Timing Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O 56F8346 Technical Data, Rev. 15 ...
Page 152
... Technical Data, Rev. 15 First Interrupt Vector Instruction Fetch First Instruction Fetch Not IRQA Interrupt Vector Max Unit See Figure 10-10, 10-11, — ns 10-12, 10-13 — ns 10-13 — ns — ns 10-13 — ns — ns 10-10, 10-11, — ns 10-12, 10-13 — ns 10-13 — ns — ns Freescale Semiconductor Preliminary ...
Page 153
... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary 1 Table 10-18 SPI Timing (Continued) Symbol Min 4 ...
Page 154
... SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) 154 SS is held High on master MSB in Bits 14– Master MSB out Bits 14 – 56F8346 Technical Data, Rev LSB in (ref Master LSB out t R Freescale Semiconductor Preliminary ...
Page 155
... SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-11 SPI Master Timing (CPHA = 1) Freescale Semiconductor Preliminary SS is held High on master MSB in Bits 14 – Master MSB out Bits 14 – 56F8346 Technical Data, Rev. 15 Serial Peripheral Interface (SPI) Timing ...
Page 156
... Figure 10-13 SPI Slave Timing (CPHA = 1) 156 ELD Slave MSB out Bits 14 – MSB in Bits 14 – ELD Slave MSB out Bits 14 – MSB in Bits 14 –1 56F8346 Technical Data, Rev ELG Slave LSB out LSB ELG Slave LSB out LSB in Freescale Semiconductor DI Preliminary ...
Page 157
... Table 10-20 Quadrature Decoder Timing Characteristic Quadrature input period Quadrature input high / low period Quadrature phase period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary Table 10-19 Timer Timing Symbol Min ...
Page 158
... The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. RXD SCI receive data pin (Input) 158 Table 10-21 SCI Timing Min BR — 0.965/BR PW 0.965/BR PW RXD PW Figure 10-16 RXD Pulse Width 56F8346 Technical Data, Rev Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-16 1.04/BR ns 10-17 Freescale Semiconductor Preliminary ...
Page 159
... JTAG Timing Characteristic TCK frequency of operation 1 using EOnCE TCK frequency of operation not 1 using EOnCE TCK clock pulse width TMS, TDI data set-up time Freescale Semiconductor Preliminary TXD PW Figure 10-17 TXD Pulse Width Table 10-22 CAN Timing Symbol Min Max BR — ...
Page 160
... Figure 10-20 Test Access Port Timing Diagram 160 Table 10-23 JTAG Timing Symbol Min — — TRST 1 )/ Input Data Valid 56F8346 Technical Data, Rev. 15 Max Unit See Figure — ns 10- 10- 10-20 — ns 10- Output Data Valid Output Data Valid Freescale Semiconductor Preliminary ...
Page 161
... Input injection current, total V current REFH ADC A current ADC B current Quiescent current Uncalibrated Gain Error (ideal = 1) Uncalibrated Offset Voltage 6 Calibrated Absolute Error Freescale Semiconductor Preliminary t TRST Figure 10-21 TRST Timing Diagram Table 10-24 ADC Parameters Symbol Min V V ADIN REFL ...
Page 162
... SINAD — THD — SFDR — ENOB — .9V in REFH 56F8346 Technical Data, Rev. 15 Typ Max Unit -0.003141 — — -17.6 — — -60 — — V REFLO 64.6 — db 59.1 — db 60.6 — db 61.1 — db 9.6 — Bits Freescale Semiconductor Preliminary ...
Page 163
... Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed Freescale Semiconductor Preliminary = 0.60V and 2.70V in 56F8346 Technical Data, Rev. 15 ...
Page 164
... Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected sampling time; 1pf Figure 10-23 Equivalent Circuit for A/D Loading 164 / 2, while the other charges to the analog input voltage. When the REFH REFH REFLO 2 S2 56F8346 Technical Data, Rev The switches switch REFH REFH 1pF Freescale Semiconductor Preliminary ...
Page 165
... IO cells as a function of capacitive load. In these cases: TotalPower = Σ((Intercept +Slope*Cload)*frequency/10MHz) where: • Summation is performed over all output pins with capacitive loads • TotalPower is expressed in mW Freescale Semiconductor Preliminary 2 *F CMOS power dissipation corresponding to the Intercept 1.3 0.11mW / pF 1.15mW ...
Page 166
... For instance, if there is a total of 8 PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. 166 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
Page 167
... D10 GPIOB0 PWMB0 37 PWMB1 PWMB2 Figure 11-1 Top View, 56F8346 144-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-1 shows the package outline for the LQFP; Table 11-1 lists the pin-out for the 144-pin LQFP. 56F8346 Technical Data, Rev. 15 56F8346 Package and Pin-Out Information ...
Page 168
... TD0 117 TD1 118 TC0 3 119 V DD_IO 120 TRST 121 TCK 122 TMS 123 TDI 124 TDO 125 126 CAN_TX 127 CAN_RX 128 V 2 CAP 129 SS0 130 SCLK0 131 MISO0 132 MOSI0 133 D11 134 D12 Freescale Semiconductor Preliminary ...
Page 169
... Package and Pin-Out Information This section contains package and pin-out information for the 56F8146. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). shows the mechanical parameters for this package, and Freescale Semiconductor Preliminary Signal Name Pin No. ...
Page 170
... Technical Data, Rev. 15 ANB4 ANB3 109 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO NC ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3 CAP EXTAL XTAL V DDA_OSC_PLL OCR_DIS Pin No. Signal Name 109 ANB5 Freescale Semiconductor Preliminary ...
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... CAP DD_IO A10 57 22 A11 58 23 A12 59 24 A13 60 25 A14 61 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name DD_IO PWMB3 75 D3 PWMB4 76 D4 PWMB5 77 D5 TXD1 78 D6 RXD1 79 OCR_DIS DDA_OSC_PLL RD 81 XTAL PS 82 EXTAL CAP GPIOD0 84 V DD_IO GPIOD1 85 RSTO ...
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... ANB0 V 105 ANB1 SS NC 106 ANB2 NC 107 ANB3 D2 108 ANB4 56F8346 Technical Data, Rev. 15 Pin No. Signal Name 134 D12 135 D13 136 D14 137 D15 138 A0 139 PHASEA0 140 PHASEB0 141 INDEX0 142 HOME0 143 EMI_MODE 144 V SS Freescale Semiconductor Preliminary ...
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... D1/2 D TOP VIEW H A SIDE VIEW PLATING BASE b METAL 0. SECTION A-A ° (ROTATED 90 ) 144 PLACES Figure 11-3 144-pin LQFP Mechanical Information Freescale Semiconductor Preliminary 0. TIPS 109 108 E1/2 E/2 VIEW VIEW B 0.1 A 144X θ SEATING PLANE ...
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... (Ψ 174 , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with a JT 56F8346 Technical Data, Rev. 15 Freescale Semiconductor Preliminary ...
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... The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs, including performance tolerances. Freescale Semiconductor Preliminary C)/W CAUTION of any ...
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... All circuitry, analog and digital, shares a common V 176 layers of the PCB with approximately 100 μF, preferably with a high-grade , V REF DDA pins. bus SS 56F8346 Technical Data, Rev. 15 and and and V pins SSA pin and cannot DDA_OSC_PLL DD_CORE Freescale Semiconductor Preliminary (GND) voltage ...
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... REFMID V REFN V REFLO V SSA_ADC Ambient Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8346VFV60 60 -40° 125° C MC56F8346MFV60 40 -40° 105° C MC56F8146VFV 60 -40° 105° C MC56F8346VFVE* 60 -40° 125° C MC56F8346MFVE* 40 -40° 105° C MC56F8146VFVE* 177 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...