MC56F8346VFVE Freescale Semiconductor, MC56F8346VFVE Datasheet - Page 149

• Manufacturer Part Number: MC56F8346VFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 62
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 144LQFP
• Family Name: 56F8xxx
• Maximum Speed: 60 MHz
• Number Of Timers: 16
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Preliminary
1. N/A, since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
Address Valid to WR Asserted
WR Width Asserted to WR Deasserted
Data Out Valid to WR Asserted
Valid Data Out Hold Time after WR
Deasserted
Valid Data Out Set-Up Time to WR
Deasserted
Valid Address after WR Deasserted
RD Deasserted to Address Invalid
Address Valid to RD Deasserted
Valid Input Data Hold after RD Deasserted
RD Assertion Width
Address Valid to Input Data Valid
Address Valid to RD Asserted
RD Asserted to Input Data Valid
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
Characteristic
Table 10-16 External Memory Interface Timing
Symbol
t
t
t
t
t
t
WRWR
t
t
t
WRRD
RDWR
t
t
t
ARDD
t
t
RDRD
ARDA
AWR
t
DWR
WAC
DOH
DOS
DRD
t
RDD
RDA
t
WR
RD
AD
56F8346 Technical Data, Rev. 15
Configuration
Wait States
WWS=0
WWS>0
WWS=0
WWS>0
WWS=0
WWS=0
WWS>0
WWS>0
WWS=0
WWS>0
WWS=0
WWS>0
-10.252
-14.414
-19.299
-12.411
-17.297
-0.357
-2.121
-1.805
-0.063
-0.253
-2.868
-9.505
-2.552
-1.512
-2.047
-9.000
-3.888
-2.922
-1.645
-2.002
-1.323
-1.442
-0.695
-0.476
-0.160
0.257
0.00
D
2
0.75 + DCAOE
0.25 + DCAOE
0.25 + DCAEO
0.25 + DCAOE
0.25 + DCAEO
0.25 + DCAOE
0.25 + DCAEO
1.25 + DCAOE
1.25 + DCAOE
0.25 + DCAEO WWSH, RWSS
0.75 + DCAEO
0.75 + DCAOE
N/A
0.50
0.50
0.00
1.00
1.00
1.00
0.00
1.00
0.00
1.00
0.50
0.00
0.50
M
0
1
External Memory Interface Timing
RWSS, RWSH
WWS, WWSS
Wait States
RWSS, RWS
RWSS, RWS
RWSS, RWS
Controls
MDAR
WWSS,
WWSS,
MDAR
WWSS
WWSS
WWSH
WWSH
WWSH
RWSH,
RWSH
RWSS
WWS
RWS
—
3, 4
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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