MC56F8346VFVE Freescale Semiconductor, MC56F8346VFVE Datasheet - Page 15

• Manufacturer Part Number: MC56F8346VFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 62
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 144LQFP
• Family Name: 56F8xxx
• Maximum Speed: 60 MHz
• Number Of Timers: 16
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.5 Product Documentation
The documents in
and 56F8146 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor sales offices, Freescale Literature Distribution Centers, or online at
http://www.freescale.com.
Freescale Semiconductor
Preliminary
DSP56800E
Reference Manual
56F8300 Peripheral User Manual
56F8300 SCI/CAN Bootloader User
Manual
56F8346/56F8146
Technical Data Sheet
Errata
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
pdb_m[15:0]
cdbw[15:0]
pab[20:0]
cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
xab1[23:0]
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
IPBus [15:0]
to 0.
Name
Topic
Program data bus for instruction word fetches or read operations.
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
Program memory address bus. Data is returned on pdb_m bus.
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
Table 1-3
are required for a complete description and proper design with the 56F8346
Table 1-3 Chip Documentation
Details any chip issues that might be present
Primary Data Memory Interface Bus
Detailed description of the 56800E family architecture,
and 16-bit controller core processor and the instruction
set
Detailed description of peripherals of the 56F8300
devices
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
Secondary Data Memory Interface
Table 1-2 Bus Signal Names
56F8346 Technical Data, Rev. 15
Program Memory Interface
Peripheral Interface Bus
Description
Function
1
, words, and long data types. Data is written
MC56F8346E
DSP56800ERM
MC56F8300UM
MC56F83xxBLUM
MC56F8346
MC56F8146E
Order Number
Product Documentation
15