DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 222

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Instruction Descriptions
2.2.58 (3)
SHAR (SHift Arithmetic Right)
Operation
Rd (right arithmetic shift)
Assembly-Language Format
SHAR.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. Bit
0 shifts into the carry flag. Bit 15 shifts into itself. Since bit 15 remains unaltered, the sign does
not change.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 206 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHAR (W)
Mnemonic
SHAR.W
MSB
b15
Rd
Operands
Rd
. . . . . .
1st byte
1
1
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 0.
2nd byte
9
Instruction Format
cleared to 0.
cleared to 0.
—
I
rd
UI H
—
LSB
b0
—
3rd byte
—
U
C
N
4th byte
Shift Arithmetic
Z
V
0
States
No. of
C
1