M3062LFGPFP#U5C Renesas Electronics America, M3062LFGPFP#U5C Datasheet - Page 181

• Manufacturer Part Number: M3062LFGPFP#U5C
• Description: IC M16C/62P MCU FLASH 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M3062LFGPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 15.22
Figure 15.23
NOTES :
i = 0 to 5
Measurement pulse
Timing at which counter
reaches “0000h”
TBiS bit
IR bit in TBiIC
register
MR3 bit in TBiMR
register
Reload register
transfer timing
NOTES :
i = 0 to 5
TBiS bit
IR bit in TBiIC
register
MR3 bit in TBiMR
register
Reload register
transfer timing
Count source
Measurement pulse
Timing at which counter
reaches “0000h”
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00b” (measure the
Jan 10, 2006
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10b” (measure the
interval from falling edge to falling edge of the measurement pulse).
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Count source
Operation Timing when Measuring a Pulse Period
Operation Timing when Measuring a Pulse Width
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to the bit 5 to bit 7 in the TABSR register.
counter
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TABSR register.
counter
“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
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“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
Set to “0” upon accepting an interrupt request or by writing in
program
Set to “0” upon accepting an interrupt request or by
writing in program
Transfer
(indeterminate
value)
(NOTE 1)
Transfer
(indeterminate value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
Transfer
(measured
value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
(NOTE 2)
(NOTE 2)
15. Timers