SAK-C164CI-8E25M DB Infineon Technologies, SAK-C164CI-8E25M DB Datasheet - Page 62
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SAK-C164CI-8E25M DB
Manufacturer Part Number
SAK-C164CI-8E25M DB
Description
IC MCU 16BIT 64KB OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C164CI-8EM_CB.pdf
(79 pages)
Specifications of SAK-C164CI-8E25M DB
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
59
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-80
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
K164CI8E25MDBNP
K164CI8E25MDBXP
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDBIN
SAKC164CI8E25MDBX
SP000104057
K164CI8E25MDBXP
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDBIN
SAKC164CI8E25MDBX
SP000104057
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 15
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
Data Sheet
Memory Cycle Variables
t
Symbol
t
t
t
t
t
t
t
t
A
5
6
7
8
9
10
11
12
+
t
CC 10 +
CC 4 +
CC 10 +
CC 10 +
CC -10 +
CC –
CC –
CC 30 +
C
+
Symbol
t
t
t
A
C
F
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
A
t
t
t
t
58
A
A
A
C
t
A
Values
TCL × <ALECTL>
2TCL × (15 - <MCTC>)
2TCL × (1 - <MTTC>)
max.
–
–
–
–
–
6
26
–
1 / 2TCL = 1 to 25 MHz
min.
TCL - 10
+
TCL - 16
+
TCL - 10
+
TCL - 10
+
-10 +
–
–
2TCL - 10
+
Variable CPU Clock
t
t
t
t
t
A
A
A
A
C
t
A
max.
–
–
–
–
–
6
TCL + 6
–
C164CL/SL
V2.0, 2001-05
C164CI/SI
Unit
ns
ns
ns
ns
ns
ns
ns
ns