SAK-C164CI-8E25M DB Infineon Technologies, SAK-C164CI-8E25M DB Datasheet - Page 76
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SAK-C164CI-8E25M DB
Manufacturer Part Number
SAK-C164CI-8E25M DB
Description
IC MCU 16BIT 64KB OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C164CI-8EM_CB.pdf
(79 pages)
Specifications of SAK-C164CI-8E25M DB
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
59
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-80
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
K164CI8E25MDBNP
K164CI8E25MDBXP
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDBIN
SAKC164CI8E25MDBX
SP000104057
K164CI8E25MDBXP
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDBIN
SAKC164CI8E25MDBX
SP000104057
AC Characteristics
CLKOUT
(Operating Conditions apply)
Parameter
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Figure 24
Notes
1)
2)
3)
4)
Data Sheet
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
Command
CLKOUT
RD, WR
CLKOUT Timing
ALE
t
Symbol
t
t
t
t
t
t
32
29
30
31
32
33
34
CC 40
CC 14
CC 10
CC –
CC –
CC 0 +
Running cycle
t
t
30
34
min.
2)
Max. CPU Clock
t
t
33
31
t
= 25 MHz
A
72
1)
max.
40
–
–
4
4
10 +
t
29
t
A
MUX/Tristate
1 / 2TCL = 1 to 25 MHz
min.
2TCL
TCL - 6
TCL - 10
–
–
0 +
Variable CPU Clock
t
A
3)
max.
2TCL
–
–
4
4
10 +
4)
C164CL/SL
V2.0, 2001-05
t
A
C164CI/SI
Unit
ns
ns
ns
ns
ns
ns