DSPIC30F2011-30I/P Microchip Technology, DSPIC30F2011-30I/P Datasheet - Page 33
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DSPIC30F2011-30I/P
Manufacturer Part Number
DSPIC30F2011-30I/P
Description
IC DSPIC MCU/DSP 12K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
7.DSPIC30F2012-30ISO.pdf
(205 pages)
Specifications of DSPIC30F2011-30I/P
Program Memory Type
FLASH
Program Memory Size
12KB (4K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Package
18PDIP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F2011-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2011-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
FIGURE 3-4:
3.1.2
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically
contain state (variable) data for DSP operations,
whereas X data space should typically contain
coefficient (constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the “16-bit MCU and DSC Programmer’s Reference
Manual” (DS70157) for details on instruction encoding.
© 2010 Microchip Technology Inc.
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
Figure
Program Memory
‘Phantom’ Byte
(read as ‘0’)
PC Address
0x000000
0x000002
0x000004
0x000006
3-5), only the lower 16 bits of the
PROGRAM DATA TABLE ACCESS (MSB)
Section 2.4 “DSP
00000000
00000000
00000000
00000000
dsPIC30F2011/2012/3012/3013
TBLRDH.B (Wn<0> = 1)
23
Note that by incrementing the PC by 2 for each
program memory word, the LS 15 bits of data space
addresses directly map to the LS 15 bits in the
corresponding
remaining bits are provided by the Program Space
Visibility Page register, PSVPAG<7:0>, as shown in
Figure
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions require one instruction
• All other instructions require two instruction cycles
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances require two instruction
• Any other iteration of the REPEAT loop allow the
Note:
cycle in addition to the specified execution time:
- MAC class of instructions with data operand
- MOV instructions
- MOV.D instructions
in addition to the specified execution time of the
instruction.
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
- Execution upon re-entering the loop after an
instruction accessing data, using PSV, to execute
in a single cycle.
16
TBLRDH.W
prefetch
interrupt
interrupt is serviced
3-5.
TBLRDH.B (Wn<0> = 0)
PSV access is temporarily disabled during
table reads/writes.
program
8
space
DS70139G-page 33
addresses.
0
The