DSPIC30F2011-30I/P Microchip Technology, DSPIC30F2011-30I/P Datasheet - Page 84
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DSPIC30F2011-30I/P
Manufacturer Part Number
DSPIC30F2011-30I/P
Description
IC DSPIC MCU/DSP 12K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
7.DSPIC30F2012-30ISO.pdf
(205 pages)
Specifications of DSPIC30F2011-30I/P
Program Memory Type
FLASH
Program Memory Size
12KB (4K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Package
18PDIP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F2011-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2011-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F2011/2012/3012/3013
11.1.2
Each capture channel has an associated FIFO buffer
which is four 16-bit words deep. There are two status
flags which provide status on the FIFO buffer:
• ICBNE – Input Capture Buffer Not Empty
• ICOV – Input Capture Overflow
The ICBNE is set on the first input capture event and
remains set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events, and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition occurs and the ICOV
bit is set to a logic ‘1’. The fifth capture event is lost and
is not stored in the FIFO. No additional events are
captured until all four events have been read from the
buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
11.1.3
The input capture module consists of up to 8 input
capture channels. Each channel can select between
one of two timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
11.1.4
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the
following operations are performed by the input capture
logic:
• The input capture interrupt flag is set on every
• The interrupt on Capture mode setting bits,
• A capture overflow condition is not generated in
DS70139G-page 84
edge, rising and falling.
ICI<1:0>, is ignored since every capture
generates an interrupt.
this mode.
CAPTURE BUFFER OPERATION
TIMER2 AND TIMER3 SELECTION
MODE
HALL SENSOR MODE
11.2
An input capture event generates a device wake-up or
interrupt, if enabled, if the device is in CPU Idle or Sleep
mode.
Independent of the timer being enabled, the input
capture module wakes up from the CPU Sleep or Idle
mode when a capture event occurs if ICM<2:0> = 111
and the interrupt enable bit is asserted. The same
wake-up can generate an interrupt if the conditions for
processing
The wake-up feature is useful as a method of adding
extra external pin interrupts.
11.2.1
CPU Sleep mode allows input capture module
operation with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable and the input
capture module can only function as an external
interrupt source.
The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111) in order for the
input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.
11.2.2
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the Interrupt
mode selected by the ICI<1:0> bits is applicable, as well
as the 4:1 and 16:1 capture prescale settings which are
defined by control bits ICM<2:0>. This mode requires
the selected timer to be enabled. Moreover, the ICSIDL
bit must be asserted to a logic ‘0’.
If
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin serves only as an external interrupt pin.
11.3
The input capture channels have the ability to generate
an interrupt based on the selected number of capture
events. The selection number is set by control
bits, ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx register.
Enabling an interrupt is accomplished via the
respective capture channel interrupt enable (ICxIE) bit.
The capture interrupt enable bit is located in the
corresponding IEC Control register.
the
Input Capture Operation During
Sleep and Idle Modes
Input Capture Interrupts
input
INPUT CAPTURE IN CPU SLEEP
MODE
INPUT CAPTURE IN CPU IDLE
MODE
the
capture
interrupt
© 2010 Microchip Technology Inc.
module
have
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