PIC18F4510-I/ML Microchip Technology, PIC18F4510-I/ML Datasheet - Page 13
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PIC18F4510-I/ML
Manufacturer Part Number
PIC18F4510-I/ML
Description
IC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F4510-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4510-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
41. Module: MSSP
EXAMPLE 6:
42. Module: Reset
© 2007 Microchip Technology Inc.
When the MSSP is configured for SPI mode, the
Buffer Full bit, BF (SSPSTAT<0>), should not be
polled in software to determine when the transfer
is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 6,
SSPSTAT is copied into the working register
where the bit test is performed.
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 25.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
occurs when a write operation is being
executed (start of a Q4 cycle).
MOVF
BTFSS
BRA
SSPSTAT, W
WREG, BF
loop_MSB
PIC18F2410/2510/4410/4510
43. Module: 10-Bit Analog-to-Digital (A/D)
When the A/D clock source is selected as 2 T
or RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 T
8 T
selecting the 2 T
Date Codes that pertain to this issue:
All engineering and production devices.
OSC
, 16 T
Converter
OSC
DL
OSC
(Differential Linearity Error) may
, 32 T
or RC modes.
OSC
, 64 T
IL
(Integral Linearity
DS80277C-page 13
OSC
) and avoid
OSC
OSC
,