PIC18F4510-I/ML Microchip Technology, PIC18F4510-I/ML Datasheet - Page 9
![IC MCU FLASH 16KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4510-I/ML
Manufacturer Part Number
PIC18F4510-I/ML
Description
IC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F4510-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4510-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
25. Module: EUSART
26. Module: EUSART
27. Module: MSSP
© 2007 Microchip Technology Inc.
In Synchronous mode, EUSART baud rates using
SPBRG values of ‘0’ and ‘1’ may not function
correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Date Codes that pertain to this issue:
All engineering and production devices.
During an auto-baud operation, the TX pin is tri-
stated. Transceivers which do not provide a pull-up
on the TX signal may cause the bus to become
inadvertently active and prevent additional bus
activity.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and the SSPOV bits. In
both situations, the SSPIF bit is not set and an
interrupt will not occur. The device will vector to the
Interrupt Service Routine only if the interrupt is
enabled and an address match occurs.
Work around
The I
I
Date Codes that pertain to this issue:
All engineering and production devices.
2
C event to maintain normal operation.
2
C slave must clear the SSPOV bit after each
2
C system with multiple slave nodes, an
PIC18F2410/2510/4410/4510
28. Module: MSSP
29. Module: MSSP
30. Module: MSSP
In I
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPADD ≥ 1.
Date Codes that pertain to this issue:
All engineering and production devices.
In I
ware to begin data reception and cleared by the
peripheral after a byte is received. After a byte is
received, the device may take up to 80 T
RCEN and 800 T
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions typically
is long enough for the RCEN bit to clear. For mul-
tiple byte receptions, the software must wait until
the bit is cleared by the peripheral before the next
byte can be received.
Date Codes that pertain to this issue:
All engineering and production devices.
Setting the SEN bit initiates a Start sequence on
the bus, after which, the SEN bit is cleared auto-
matically by hardware. If the SEN bit is set again
(without an address byte being transmitted), a
Start sequence will not commence and the SEN bit
will not be cleared. This condition causes the bus
to remain in an active state. The system is idle
when ACKEN, RCEN, PEN, RSEN, and SEN are
clear.
Work around
Set the PEN or RSEN bit to transmit a Stop or
Repeated Start sequence, although the SEN bit
may still be set, indicating the bus is active. After
the sequence has completed, the PEN, RSEN and
SEN bit will be clear, indicating the bus is idle.
Clearing and setting the SSPEN bit will also reset
the I
SEN Status bits.
Date Codes that pertain to this issue:
All engineering and production devices.
2
2
C Master mode, the BRG value of ‘0’ may not
C Master mode, the RCEN bit is set by soft-
2
C peripheral and clear the PEN, RSEN and
CY
during emulation.
DS80277C-page 9
CY
to clear