DSPIC30F3010-20I/ML Microchip Technology, DSPIC30F3010-20I/ML Datasheet - Page 107
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DSPIC30F3010-20I/ML
Manufacturer Part Number
DSPIC30F3010-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3010-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301020IML
16.0
The Serial Peripheral Interface (SPI) module is a
synchronous
communicating with other peripheral devices, such as
EEPROMs, shift registers, display drivers and A/D
converters or other microcontrollers. It is compatible
with SPI and SIOP interfaces available on some other
microcontrollers.
16.1
The SPI module consists of a 16-bit shift register,
SPI1SR, used for shifting data in and out, and a buffer
register, SPI1BUF. A Control register, SPI1CON,
configures the module. Additionally, a status register,
SPI1STAT, indicates various status conditions.
The serial interface consists of 4 pins: SDI1 (Serial
Data Input), SDO1 (Serial Data Output), SCK1 (Shift
Clock Input or Output) and SS1 (Active-Low Slave
Select).
In Master mode operation, SCK1 is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shifts
out bits from the SPI1SR to the SDO1 pin and
simultaneously shifts in data from the SDI1 pin. An
interrupt is generated when the transfer is complete
and the corresponding interrupt flag bit (SPI1IF) is set.
This interrupt can be disabled through an interrupt
enable bit (SPI1IE).
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPI1SR to SPI1BUF.
If the receive buffer is full when new data is being
transferred from SPI1SR to SPI1BUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is ‘1’, effectively disabling the module until
SPI1BUF is read by user software.
Transmit writes are also double-buffered. The user
writes to SPI1BUF. When the master or slave transfer
is completed, the contents of the shift register
(SPI1SR) are moved to the receive buffer. If any trans-
mit data has been written to the buffer register, the
© 2010 Microchip Technology Inc.
Note:
SPI MODULE
Operating Function Description
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
serial
interface.
It
is
useful
for
contents of the transmit buffer are moved to SPI1SR.
The received data is thus placed in SPI1BUF and the
transmit data in SPI1SR is ready for the next transfer.
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPI1BUF. The interrupt is generated
at the middle of the transfer of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCKx. Again, the
interrupt is generated when the last bit is latched. If
SSx control is enabled, then transmission and
reception are enabled only when SSx = low. The
SDOx output will be disabled in SSx mode with SSx
high.
The clock provided to the module is (F
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
16.1.1
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation, except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit 15 of
the SPIxSR for 16-bit operation. In both modes, data is
shifted into bit 0 of the SPIxSR.
16.1.2
A control bit, DISSDO, is provided to the SPI1CON
register to allow the SDO1 output to be disabled. This
will allow the SPI module to be connected in an input
only configuration. SDOx can also be used for general
purpose I/O.
Note:
dsPIC30F3010/3011
Both the transmit buffer (SPI1TXB) and
the receive buffer (SPI1RXB) are mapped
to the same register address, SPI1BUF.
WORD AND BYTE
COMMUNICATION
SDO1 DISABLE
DS70141F-page 107
OSC
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