PIC18LF2431-I/SP Microchip Technology, PIC18LF2431-I/SP Datasheet - Page 178

• Manufacturer Part Number: PIC18LF2431-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2431-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

PIC18F2331/2431/4331/4431
FIGURE 16-13:
16.2.6.2
The velocity event pulse (velcap, see Figure 16-12)
serves as the TMR5 capture trigger to IC1 while in the
Velocity mode. The number of velocity events are
reduced by the velocity postscaler before they are used
as the input capture clock. The velocity event reduction
ratio can be set with the PDEC1:PDEC0 control bits
(QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1).
The velocity postscaler settings are automatically
reloaded from their previous values as the Velocity
mode is re-enabled.
DS39616C-page 176
Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio
QEA
QEB
vel_out
velcap
TMR5
VELR
cnt_reset
IC1IF
CAP1REN
Instr.
Execution
2: VELR register latches the TMR5 count on the “velcap” capture pulse. Timer5 must be set to the Synchronous Timer or
3: The TMR5 counter is reset on the next Q1 clock cycle following the “velcap” pulse. TMR5 value is unaffected when
4: IC1IF interrupt is enabled by setting IC1IE as follows: BSF PIE2, IC1IE. Assume IC1E bit is placed in PIE2
5: Post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1).
is set to divide by 4 (PDEC<1:0> = 01).
Counter mode. In this example, it is set to the Synchronous Timer mode, where the TMR5 prescaler divide ratio = 1
(i.e., Timer5 clock = T
the Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be reconfigured to
their previous settings when re-entering Velocity Measurement mode. While making speed measurements of very
slow rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode may not provide
sufficient precision. The Pulse-Width Measurement mode may have to be used to provide the additional precision.
In this case, the input pulse is measured on the CAP1 input pin.
Peripheral Interrupt Enable register in the target device. The actual IC1IF bit is written on Q2 rising edge.
(4)
(2)
(2)
Velocity Postscaler
(3)
BCF T5CON, VELM
VELOCITY MEASUREMENT TIMING
Old Value
CY
BCF PIE2, IC1IE
).
Q1
BSF PIE2, IC1IE
Preliminary
Forward
1529
Q1
16.2.6.3
The TMR5 value can be reset (TMR5 register
pair = 0000h) on a velocity event capture by setting
the CAP1REN bit (CAP1CON<6>). When CAP1REN
is cleared, the TMR5 time base will not be reset on
any velocity event capture pulse. The VELR register
pair, however, will continue to be updated with the
current TMR5 value.
(1)
MOVWF QEICON
1537
Reverse
CAP1REN in Velocity Mode
(5)
Q1
© 2007 Microchip Technology Inc.