PIC18LF2431-I/SP Microchip Technology, PIC18LF2431-I/SP Datasheet - Page 238

• Manufacturer Part Number: PIC18LF2431-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2431-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

PIC18F2331/2431/4331/4431
To set up an Asynchronous Transmission:
1.
2.
3.
4.
FIGURE 19-6:
TABLE 19-6:
DS39616C-page 236
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend:
Name
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit, BRGH (see Section 19.2 “EUSART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
Note:
RX (Pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous reception.
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH
CSRC
SPEN
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after
the third word, causing the OERR (Overrun) bit to be set.
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
ASYNCHRONOUS RECEPTION
bit
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
bit 1
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
Stop
Preliminary
bit
ADDEN
SENDB
BRG16
Word 1
RCREG
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
Start
bit
bit 0
TMR0IF
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
BRGH
FERR
Bit 2
—
Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREG register (starts
transmission).
INT0IF
OERR
TRMT
WUE
bit 7/8
Bit 1
Word 2
RCREG
Stop
bit
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF
Start
bit
© 2007 Microchip Technology Inc.
0000 000x
-000 0000
-000 0000
-111 1111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit 7/8
Stop
0000 000u
-000 0000
-000 0000
-111 1111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
bit
Value on
all other
Resets