PIC18LF2523-I/SP Microchip Technology, PIC18LF2523-I/SP Datasheet - Page 26
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PIC18LF2523-I/SP
Manufacturer Part Number
PIC18LF2523-I/SP
Description
IC PIC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF2523-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx12-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2423/2523/4423/4523
TABLE 5-3:
DS39759A-page 26
MCLRE
LPT1OSC
PBADEN
CCP2MX
DEBUG
XINST
LVP
STVREN
CP3
CP2
CP1
CP0
CPD
CPB
WRT3
Bit Name
PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG5H
CONFIG5H
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG5L
CONFIG5L
CONFIG5L
CONFIG5L
CONFIG6L
Words
MCLR Pin Enable bit
1 = MCLR pin enabled, RE3 input pin disabled
0 = RE3 input pin enabled, MCLR pin disabled
Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
PORTB A/D Enable bit
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled
Low-Voltage Programming Enable bit
1 = Low-Voltage Programming enabled, RB5 is the PGM pin
0 = Low-Voltage Programming disabled, RB5 is an I/O pin
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Code Protection bits (Block 3 code memory area)
1 = Block 3 is not code-protected
0 = Block 3 is code-protected
Code Protection bits (Block 2 code memory area)
1 = Block 2 is not code-protected
0 = Block 2 is code-protected
Code Protection bits (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
Code Protection bits (Block 0 code memory area)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
Code Protection bits (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
Code Protection bits (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
Write Protection bits (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-protected
purpose I/O pins
Debug
(Legacy mode)
Description
© 2005 Microchip Technology Inc.