PIC18LF2523-I/SP Microchip Technology, PIC18LF2523-I/SP Datasheet - Page 8
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PIC18LF2523-I/SP
Manufacturer Part Number
PIC18LF2523-I/SP
Description
IC PIC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF2523-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx12-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2423/2523/4423/4523
2.6
When the LVP Configuration bit is ‘1’ (see Section 5.3
“Single-Supply
Low-Voltage ICSP mode is enabled. As shown in
Figure 2-9, Low-Voltage ICSP Program/Verify mode is
entered by holding PGC and PGD low, placing a logic
high on PGM and then raising MCLR/V
In this mode, the RB5/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin. Figure 2-10 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-9:
FIGURE 2-10:
DS39759A-page 8
MCLR/V
V
PGM
PGD
PGC
MCLR/V
V
PGM
PGD
PGC
DD
DD
Entering and Exiting Low-Voltage
ICSP Program/Verify Mode
PP
PP
V
/RE3
IH
/RE3
ICSP
PGD = Input
V
PGD = Input
ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
IH
EXITING LOW-VOLTAGE
PROGRAM/VERIFY MODE
P15
V
P16
IH
Programming”),
P12
V
P18
IH
PP
/RE3 to V
the
IH
.
command, PGC is cycled four times. The commands
2.7
The PGC pin is used as a clock input pin and the PGD pin
is used for entering command bits and data input/output
during serial operation. Commands and data are trans-
mitted on the rising edge of PGC, latched on the falling
edge of PGC and are Least Significant bit (LSb) first.
2.7.1
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
needed for programming and verification are shown in
Table 2-4.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-5. The 4-bit
command is shown Most Significant bit (MSb) first. The
command operand, or “Data Payload”, is shown
<MSB><LSB>. Figure 2-11 demonstrates how to
serially present a 20-bit command/operand to the
device.
2.7.2
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
TABLE 2-4:
TABLE 2-5:
Core Instruction
(Shift in16-bit instruction)
Shift out TABLAT register
Table Read
Table Read, post-increment
Table Read, post-decrement
Table Read, pre-increment
Table Write
Table Write, post-increment by 2
Table Write, start programming,
post-increment by 2
Table Write, start programming
Command
1101
4-Bit
Serial Program/Verify Operation
4-BIT COMMANDS
CORE INSTRUCTION
Description
Payload
3C 40
Data
COMMANDS FOR
PROGRAMMING
SAMPLE COMMAND
SEQUENCE
© 2005 Microchip Technology Inc.
Table Write,
post-increment by 2
Core Instruction
Command
0000
0010
1000
1001
1010
1011
1100
1101
1110
1111
4-Bit