PIC18LF2523-I/SP Microchip Technology, PIC18LF2523-I/SP Datasheet - Page 237
![IC PIC MCU FLASH 16KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2523-I/SP
Manufacturer Part Number
PIC18LF2523-I/SP
Description
IC PIC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF2523-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx12-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2423-ISP PDF datasheet #2
- PIC18F2423-ISP PDF datasheet #3
- PIC18F2423-ISP PDF datasheet #4
- PIC18F2523-ISO PDF datasheet #5
- Current page: 237 of 392
- Download datasheet (7Mb)
19.6
Figure 19-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 19-5 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 19-4:
FIGURE 19-5:
© 2007 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
T
AD
Set GO/DONE bit
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
1
acquisition time before the conversion starts.
– T
T
ACQT
A/D Conversions
Acquisition
AD
Automatic
2
Time
T
AD
Cycles
1 T
3
Conversion starts
b11
AD
A/D CONVERSION T
A/D CONVERSION T
2 T
4
AD
b10
1
3 T
Conversion starts
(Holding capacitor is disconnected)
Points to end of T
AD
b11
b9
2
4 T
b10
AD
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
3
b8
5 T
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
PIC18F2423/2523/4423/4523
AD
AD
b9
AD
4
b7
ACQT
6 T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
b8
5
AD
period (current black arrow)
b6
7 T
T
b7
6
AD
AD
b5
8
Cycles
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
19.7
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity-
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
b6
7
Note:
T
CY
AD
b4
wait is required before the next acquisition can
9 T
b5
8
Discharge
AD
b3
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 3 T
enabling the A/D before beginning an
acquisition and conversion cycle.
10
b4
9
T
AD
b2
11
10
b3
T
ACQ
ACQ
AD
b1
11
b2
12
= 0)
= 4 T
T
AD
b0
12
b1
13
AD
DS39755B-page 235
)
T
Discharge
(typically 200 ns)
b0
13
AD
1
T
Discharge
(typically
200 ns)
AD
AD
1
after
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