ATMEGA325P-20AU Atmel, ATMEGA325P-20AU Datasheet - Page 76
ATMEGA325P-20AU
Manufacturer Part Number
ATMEGA325P-20AU
Description
IC MCU AVR 32K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA325P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Rom Size
1 KB
Height
1 mm
Length
14 mm
Supply Voltage (max)
5.5 V, 5.8 V
Supply Voltage (min)
2.4 V, 2.7 V
Width
14 mm
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA325P-16AU
ATMEGA325P-16AU
ATMEGA325P-16AU
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ATmega325P/3250P
• XCK/AIN0/PCINT2 – Port E, Bit 2
XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is
output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 oper-
ates in synchronous mode.
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
• TXD/PCINT1 – Port E, Bit 1
TXD0, UART0 Transmit pin.
PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source.
• RXD/PCINT0 – Port E, Bit 0
RXD, USART0 Receive pin. Receive Data (Data input pin for the USART0). When the USART0
Receiver is enabled this pin is configured as an input regardless of the value of DDE0. When the
USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source.
Table 13-9
shown in
Table 13-9.
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. CKOUT is one if the CKOUT Fuse is programmed
Figure 13-5 on page
and
Overriding Signals for Alternate Functions PE7:PE4
Table 13-10
PE7/PCINT7
0
CKOUT
0
1
CKOUT
clk
–
PCINT7 • PCIE0
1
PCINT7 INPUT
–
I/O
(1)
(1)
relates the alternate functions of Port E to the overriding signals
69.
PE6/DO/
PCINT6
0
0
0
0
USI_THREE-
WIRE
DO
–
PCINT6 • PCIE0
1
PCINT6 INPUT
–
PE5/DI/SDA/
PCINT5
USI_TWO-WIRE
0
USI_TWO-WIRE
(SDA + PORTE5) •
DDE5
USI_TWO-WIRE •
DDE5
0
0
(PCINT5 • PCIE0)
+ USISIE
1
DI/SDA INPUT
PCINT5 INPUT
–
PE4/USCK/SCL/
PCINT4
USI_TWO-WIRE
0
USI_TWO-WIRE
(USI_SCL_HOLD
+ PORTE4) •
DDE4
USI_TWO-WIRE •
DDE4
0
USITC
(PCINT4 • PCIE0)
+ USISIE
1
USCKL/SCL
INPUT
PCINT4 INPUT
–
8023F–AVR–07/09
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