DSPIC30F5016-30I/PT Microchip Technology, DSPIC30F5016-30I/PT Datasheet - Page 158

• Manufacturer Part Number: DSPIC30F5016-30I/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5016-30I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501630IPT

dsPIC30F5015/5016
21.8
The analog input model of the 10-bit ADC is shown in
Figure 21-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
V
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
analog output source impedance (R
impedance (R
(R
required to charge the capacitor C
impedance must therefore be small enough to fully
charge the holding capacitor within the chosen sample
time. To minimize the effects of pin leakage currents on
the accuracy of the ADC, the maximum recommended
source impedance, R
to 500 ksps and a maximum of 500Ω for conversion
rates up to 1 Msps. After the analog input channel is
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 21-3:
DS70149D-page 158
DD
SS
and the holding capacitor charge time.
) impedance combine to directly affect the time
ADC Acquisition Requirements
Note: C
IC
), and the internal sampling switch
Legend: C
VA
PIN
HOLD
S
Rs
, is 5 kΩ for conversion rates up
ADC CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
V
I leakage
R
R
C
) must be allowed to fully
ANx
PIN
T
IC
SS
HOLD
C
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
HOLD
S
various junctions
), the interconnect
. The combined
V
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
± 500 nA
IC
≤ 250Ω
The user must allow at least 1 T
time, T
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the ADC. In an
automatic configuration, the user must allow enough
time between conversion triggers so that the minimum
sample time can be satisfied. Refer to Table 24-40 for
T
AD
and sample time requirements.
SAMP
Sampling
Switch
R
, between conversions to allow each sam-
SS
PIN
R
negligible if Rs ≤ 5 kΩ.
SS
V
SS
C
= DAC capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
© 2008 Microchip Technology Inc.
AD
period of sampling